SCAS802 Search Results

A115-A

Abstract: C101 SN74SSTU32864E SN74SSTU32864EZKER
Contextual Info: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2

DDR2 sdram pcb layout guidelines

Abstract: DDR2 SDRAM with SSTL_18 interface SSTL18
Contextual Info: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2

Contextual Info: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2

Contextual Info: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2

A115-A

Abstract: C101 SN74SSTU32864E SN74SSTU32864EZKER ddr2 DIMM PCB
Contextual Info: SN74SSTU32864E 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS www.ti.com SCAS802 – JULY 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2

SB865A

Abstract: SB866A ddr2 PLL JESD82 SSTUx32864 SSTU32868 JEDEC DDR2-400 2rx8 SB866 SN74SSTUB32866
Contextual Info: Application Report SCAA101 – March 2009 DDR2 Memory Interface Clocks and Registers – Overview Christian Schmoeller . CDC - Clock Distribution Circuits ABSTRACT This application report gives an overview of the existing JEDEC DDR2 Register and