QL3060 Search Results

208-PIN

Abstract: 456-PIN
Contextual Info: QL3060 - pASIC 3 FPGATM 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3060 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over

Contextual Info: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 60,000 usable PLD gates, 316 I/O pins S High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 250 MHz, data path speeds over 275 MHz

AE21 ARRAY DIODE

Abstract: QL3060 AD 149 AE9 AA23 PQ208 QL3060-1PB456C QL3060-1PQ208C B14 ON
Contextual Info: QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths

Contextual Info: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA March, 1998 2 … 60,000 usable PLD gates, 316 I/O pins High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 250 MHz, data path speeds over 275 MHz

CI 3060 elsys

Abstract: QL3060 PB256 PQ208 QL3040 QL3040-1PQ208C 344RAM
Contextual Info: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA February, 1998 2 … 60,000 usable PLD gates, 316 I/O pins 25,344 bit RAM Option High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os

CI 3060 elsys

Abstract: AA23 QL3060 QL3060-1PB456C QL3060-1PQ208C
Contextual Info: QL3060 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 4 pASIC 3 HIGHLIGHTS … 60,000 usable PLD gates, 316 I/O pins High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

A23 862-1

Abstract: AD 149 AE9 CI 3060 elsys AA23 PQ208 QL3060 QL3060-1PB456C QL3060-1PQ208C
Contextual Info: QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths

Contextual Info: QL3060 - pASIC 3 FPGATM 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density last updated 5/15/2000 QL3060 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os

Contextual Info: QL3060 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 60,000 usable PLD gates, 316 I/O pins S High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

QL3004

Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040
Contextual Info: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights • High performance over 400 MHz • 100% routability and pin stability • Instant-On capability • High security and reliability • Low power

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

208CQFP

Contextual Info: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

asynchronous fifo vhdl

Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Contextual Info: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com

pasic 3

Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
Contextual Info: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths

FPGA 144 CPGA ASIC

Abstract: QL5032 144TQFP PACKAGE 160-CQFP PLCC 144
Contextual Info: p ASIC QUICKLOGIC DEVELOPMENT TOOLS Part Number Product Name QS-QWK-PC QuickWorks QS-QTL-WS QuickTools for Workstations N/A QuickWorks - Lite N/A QuickMap QT-DFP-PC-A 1 DeskFab Programmer Kit N/A Synosys Interface Kit N/A Viewlogic Interface Kit N/A Mentor Interface Kit

84-PIN

Abstract: 84-PLCC
Contextual Info: QL2005  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

100TQFP

Abstract: 344RAM QL3040
Contextual Info: QL2003  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

QL4090

Contextual Info: QL12X16B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …2,000 usable ASIC gates, 88 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

Contextual Info: QuickSheet#3 Military Plastic Families High Performance Guaranteed Over the Military Temperature Range Military Plastic Highlights • pASIC 1, pASIC 2, pASIC 3, and QuickRAM™ families •200+MHz •Up to 176,000 usable system gates •Up to 25k bits dual-port embedded RAM

QL3012

Abstract: QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction
Contextual Info: QuickLogic Military FPGA Introduction Military FPGA Combining High Performance and High Density Military FPGA Introduction DEVICE HIGHLIGHTS Device Highlights Military FPGA • Mil Std 883 and Mil Temp Ceramic ■ Mil Temp Plastic Guaranteed -55 to +125oC

144-TQFP

Abstract: 256PBGA CPGA QL3012 QL3025 QL3040 QL3060 144TQFP 100-TQFP
Contextual Info: pASIC pASIC DEVELOPMENT TOOLS Part Number Product Name QS-QWK-PC QuickWorks QS-QTL-PC QuickTools-PC Plus QS-QTL-WS QuickTools for Workstations N/A QuickChip N/A QuickMap QT-DFP-PC-A 1 DeskFab Programmer Kit N/A Synosys Interface Kit N/A Viewlogic Interface Kit

Contextual Info: QL3040 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 40,000 usable PLD gates, 252 I/O pins S High Performance and High Density -40,000 Usable PLD Gates with 252 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

ulc xc3030

Abstract: PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
Contextual Info: ULC Reference Guide This reference guide lists most devices available for conversion. This list is not exhaustive, as new devices are added regularly. Additional devices not shown in this list may also be supported. Updated versions are available on the TEMIC web site. Check with factory if

intel 4040

Abstract: QL3004 transistor equivalent table 557 cmos 4040 datasheet general cross references QL5064 QL4009 QL4016 QL4058 QL5030
Contextual Info: EMBEDDED STANDARD PRODUCT A GENERATION AHEAD ! The Vialink Antifuse in 0.35µ µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040