RN0804
Abstract: PD0302 68040 93CS06 RN0801 PD0501 c14 c13 PD0201 PU0201 PU0203
Text: 1 2 ADS~ LW/R BLAST~ READYO~ TS~ TIP~ BB~ LOCK040~ PU0201 A 1 2 3 4 5 6 7 8 9 10 VCC 3 RN0801 COM IN IN IN IN IN IN IN IN IN PU0202 PU0203 PU0301 PU0302 PU0303 PU0304 PU0305 PU0306 PU0307 1 2 3 4 5 6 7 8 9 10 VCC 4 RN0802 COM IN IN IN IN IN IN IN IN IN PU0601
|
Original
|
PDF
|
LOCK040~
PU0201
RN0801
PU0202
PU0203
PU0301
PU0302
PU0303
PU0304
PU0305
RN0804
PD0302
68040
93CS06
RN0801
PD0501
c14 c13
PD0201
PU0201
PU0203
|
la1 d22
Abstract: La2 D22 C0301 k16 a21 LD11 LD12 LD17 LD18 LD19 68040 PST0
Text: 1 2 3 4 5 6 7 8 VCC 1 R0301 100 A 2 1 VCC C0301 22uF B PCLK BCLK2 R9 R7 T5 S6 S7 PU0301 PU0302 RSTI~ T8 T7 T6 T11 IPL0~ IPL1~ IPL2~ AVEC~ T12 S12 PD0301 PD0302 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
|
Original
|
PDF
|
R0301
C0301
PU0301
PU0302
PD0301
PD0302
PCI9060/68040
la1 d22
La2 D22
C0301
k16 a21
LD11
LD12
LD17
LD18
LD19
68040 PST0
|
PU0313
Abstract: D0301 pin DIAGRAM OF IC 7474 108 to 174 mhz C0301 LD11 LD12 LD17 LD18 la3 d20
Text: 1 2 3 4 5 6 7 8 VCC 1 R0301 100 2 1 VCCPLL VCC A C0301 22uF A 2 7 U0302 NC VCC GND OUT 14 8 VCC CLKIN OSCILLATOR 33.33 MHZ 87 85 91 182 184 40 181 PU0301 RESET~ READY960~ BTERM~ BOFF960~ HOLD960 INTUART~ INT596~ INT9060~ 93 94 95 100 101 102 106 107 108 PU0302
|
Original
|
PDF
|
R0301
C0301
U0302
PU0301
READY960~
BOFF960~
HOLD960
INT596~
INT9060~
PU0302
PU0313
D0301
pin DIAGRAM OF IC 7474
108 to 174 mhz
C0301
LD11
LD12
LD17
LD18
la3 d20
|
c14 c13
Abstract: PD0206
Text: 1 2 ADS~ LW/R BLAST~ PU0201 PU0202 PU0203 PU0301 PU0401 PU0501 A 1 2 3 4 5 6 7 8 9 10 VCC 3 RN0701 COM IN IN IN IN IN IN IN IN IN 4 1 2 3 4 5 6 7 8 9 10 PD0201 PD0202 PD0203 PD0204 PD0205 PD0206 PD0207 5 RN0702 COM IN IN IN IN IN IN IN IN IN 8 COM IN IN IN
|
Original
|
PDF
|
PU0201
PU0202
PU0203
PU0301
PU0401
PU0501
RN0701
PD0201
PD0202
PD0203
c14 c13
PD0206
|
MSL260G
Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Text: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)
|
Original
|
PDF
|
PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
MSL260G
MSL-260-G
D0806
R0807
T0803
D0802
D0807
RDD0804
D0808
5 pin reset ic ARB
|
la1 d22
Abstract: la2 d2 timer rn0805 U0301 L16 eeprom 80960CA LD11 LD12 U0101 PCI9060 68040
Text: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH
|
Original
|
PDF
|
U0101
PCI9060,
80960CA
U0102
20V8R
PCI9060
PCI9060/68040
la1 d22
la2 d2 timer
rn0805
U0301
L16 eeprom
LD11
LD12
U0101
PCI9060 68040
|
R0302
Abstract: u0304 R0303 R0304 O17-I 74F04 R0305 RASH r0308 215A1
Text: 1 2 3 4 5 6 7 8 VCC 1 7 U0301 NC VCC GND OUT 14 8 2 3 4 5 6 7 8 9 CLK33 OSCILLATOR 33 MHz A 1 19 PD0301 U0302 R0301 1 2 15 BCLK1 R0302 1 2 15 BCLK2 R0303 1 2 15 BCLK3 R0304 1 2 15 BCLK4 R0305 1 2 15 G1 G2 BCLK5 R0306 1 2 15 74FCT541AT R0307 1 2 15 A1 A2 A3
|
Original
|
PDF
|
U0301
U0302
PD0301
R0301
R0302
R0303
R0304
R0305
R0306
74FCT541AT
R0302
u0304
R0303
R0304
O17-I
74F04
R0305
RASH
r0308
215A1
|
mah8
Abstract: MDL22 u0502a LD11 LD12 U0101 RN05 RN0501 U0302
Text: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH 7
|
Original
|
PDF
|
U0101
PCI9060,
9060/DRAM
U0102
20V8R
PCI9060
PCI9060/DRAM
mah8
MDL22
u0502a
LD11
LD12
U0101
RN05
RN0501
U0302
|
D0807
Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Text: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors
|
Original
|
PDF
|
PCI9060
PCI9060,
80960CA
82596CA
U0101
20V8R
U0102
PCI9060
D0807
C0702
D0801
D0806
R0807
T0803
D0808
D0802
RDD0804
C0705
|
16V8-10
Abstract: U0801A
Text: PowerPC 403 to PCI 9060ES Application Note PCI 9060/403 AN May 10, 1996 Version 0.4 PowerPC 403 to PCIbus Application Note Features_ • • • • Embedded system containing PowerPC 403 with a PCIbus interface PCI 9060ES chip supports master, slave and PCI
|
Original
|
PDF
|
9060ES
9060ES
403local
403GC
PCI9060ES
100ns
150ns
200ns
16V8-10
U0801A
|
68040* part numbering
Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Text: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _
|
Original
|
PDF
|
PCI9060/68040
PCI9060
32-bit
PCI9060,
100ns
200ns
300ns
68040* part numbering
93CS46
SR96
L16 eeprom
Motorola 68040
Pal programming
10B5
|
u0304
Abstract: 16V8-10 LA29 LA30 LA25 16v810 R0302 PD0301
Text: LA[2.31] LA[2.31] U0301 LA24 LA25 LA26 LA27 LBE0~ LBE1~ LBE2~ LBE3~ A7 (A6) (A5) (A4) LBE0~ LBE1~ LBE2~ LBE3~ LHOLD HOLDACK CS1~ XACK~ LHOLD HOLDACK CS1~ XACK~ LCLKB LRESET~ ADS~ LW/R BLAST~ RDYO~ LCLKB LRESET~ ADS~ LW/R BLAST~ RDYO~ ADS~ BLAST~ READY
|
Original
|
PDF
|
U0301
CS9060~
PD0301
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
u0304
16V8-10
LA29
LA30
LA25
16v810
R0302
PD0301
|
R0801
Abstract: U0801A
Text: +5V +5V +5V RN0701 1 2 3 4 5 6 7 8 9 10 ADS~ BLAST~ LW/R CS1~ PR/W WBE0~ WBE1~ WBE2~ WBE3~ RN0702 COM IN IN IN IN IN IN IN IN IN 1 2 3 4 5 6 7 8 9 10 PU0101 PU0102 PU0103 PU0104 PU0202 PU0203 PU0204 PU0205 RN0703 COM IN IN IN IN IN IN IN IN IN RN9R10P10K 1
|
Original
|
PDF
|
RN0701
RN0702
PU0101
PU0102
PU0103
PU0104
PU0202
PU0203
PU0204
PU0205
R0801
U0801A
|
16V8-10
Abstract: semiconductor ad 5.9 u0304 R0801 74ACT74 LD11 LD12 U0801A LA17 MXA0 A10
Text: ECN HISTORY |LINK |N2.SCH |N3.SCH |N4.SCH |N5.SCH |N6.SCH |N7.SCH SPARE GATES: DESCRIPTION DATE REV 1 - 01/24/96 REV 2 -CHANGED DRMMUX 2/17/96 APPROVAL PU0101 1 PU0102 PU0103 12 11 D P R U0303B Q 9 CLK C L 1 3 Q 8 74ACT74 PU0104 APPROVALS DATE PLX TECHNOLOGY
|
Original
|
PDF
|
PU0101
PU0102
PU0103
U0303B
74ACT74
PU0104
POWERPC/PCI9060ES
220uF
16V8-10
semiconductor ad 5.9
u0304
R0801
74ACT74
LD11
LD12
U0801A
LA17
MXA0 A10
|
|
16V8-10
Abstract: PCIbus 16V8 403GA 403GC 9060ES MACH210 MACH210A PCI9060ES MXA0 A10
Text: Go to next Section: Using the PCI 9060 w/o CPU Return to Table of Contents PowerPC 403 to PCI 9060ES Application Note PCI 9060/403 AN May 10, 1996 Version 0.4 PowerPC 403 to PCIbus Application Note Features_ • • • • Embedded system containing PowerPC 403 with a
|
Original
|
PDF
|
9060ES
9060ES
403local
403GC
PCI9060ES
100ns
150ns
200ns
16V8-10
PCIbus
16V8
403GA
MACH210
MACH210A
MXA0 A10
|
1N4148/2 pin connector sip
Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Text: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000
|
Original
|
PDF
|
PCI9060
0x00000000
0x00000002
0x00000004
100ns
200ns
300ns
80960CA)
PCLK1-33
1N4148/2 pin connector sip
ACT04 MOTOROLA
1N4148 D0805
pal programming
sw dip-3
80960CA
15 pin through hole d sub connector
16v8h
DIODE MOTOROLA B33
D0805
|
10B5
Abstract: 93CS46
Text: Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • •
|
Original
|
PDF
|
PCI9060/68040
PCI9060
32-bit
PCI9060,
100ns
200ns
300ns
10B5
93CS46
|
code h7f
Abstract: datasheet LD9 m mah8 MDL22 MDL14 fuse 9060ES A3-12 LD11 MACH210A U0101
Text: Go to next Section: PowerPC 403 to PCI 9060ES Return to Table of Contents Designing a PCI Memory Board No CPU, DRAM Control examples PLX PCI9060 DRAM Controller Application Note Revision 1.0 September 8, 1995 PLX Technology, Inc. 625 Clyde Avenue, Mt View, California 94043
|
Original
|
PDF
|
9060ES
PCI9060
9060/DRAM
100ns
150ns
PCI9060
BCLK-33
code h7f
datasheet LD9 m
mah8
MDL22
MDL14 fuse
9060ES
A3-12
LD11
MACH210A
U0101
|
D0802
Abstract: D0807 C0702 16v8c T0803 D0806 R0807 D0808 RDD0804 pt3868
Text: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 20V8R DIP 9 U0102 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11
|
Original
|
PDF
|
U0101
20V8R
U0102
PCI9060,
80960CA
82596CA
PCI9060
PCI9060
D0802
D0807
C0702
16v8c
T0803
D0806
R0807
D0808
RDD0804
pt3868
|