PSD413 Search Results

WSI PSD813F

Abstract: PSD413A1 PSD413A2 PSD813F PSD813F1
Contextual Info: Document: WSI-1018 April 27, 1998 Subject: End of Life Notification Devices: Multi-Chip Module PSD413F Devices Please discontinue use and move to OTP PSD413 Family or FLASH PSD813F Family Dear WSI Customer, Due to very limited demand, WSI is announcing the immediate obsolescence of the following MultiChip Module Devices:

683XX

Abstract: 68HC11 68HC16 A15F PSD411A1 PSD411A2 psd4xx flip flop T
Contextual Info: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s

Avance Logic

Abstract: Z80 CPU APD Arrays Avance Logic A15F PIN DIAGRAM OF 80186 683XX 68HC11 68HC16 PSD411A1 PSD411A2
Contextual Info: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s

psd4xx

Abstract: psd3xx psd5xx
Contextual Info: PSD3xx PSD4xx PSD413F PSD5xx ZPSD3xx ZPSD4xx ZPSD5xx

crystal 11.059MHZ

Abstract: HC16201-a HC16201 psdsoft express 8.6 ZENER A20 DK4000 2N39 DK-4000 14 pin single in line connector 167CR
Contextual Info: DK4000-XA DEVELOPMENT KIT For PSD4000 Series of Flash PSDs Rev 0.98 Contents: ™ ™ ™ ™ ™ ™ ™ PSDsoft Express - Point and Click Windows based Development Software DK4000 Eval Board with PSD4135G2 FlashLINK JTAG In-System Programmer ISP Ribbon and "Flying Lead" JTAG cables for FlashLINK

A15F

Abstract: PSDsoft object file to hex file conversion Magic*PRO III psd4xx 80C31 PSD413A2 wsi Required Programming Algorithm Change
Contextual Info: Programmable Peripheral Application Note 047 Designing with the PSD413F – A PSD with Flash Memory By Ching Lee Introduction The PSD413F is the first member of the PSD family that supports In-System Programming ISP of the main program memory. The architecture is based on the PSD4XX core with

Contextual Info: PSD413F Family PSD413F Pin Assignments Pin Ho. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 68-Pin PLDCC Package GND ADIO_7 ADIO_6 ADIO_5 ADIO_4 ADIO_3 ADIO_2 ADIO_1 ADIO_0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO v cc

ST 9427

Abstract: 52SB
Contextual Info: PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs PRELIMINARY DATA FEATURES SUMMARY • 5 V±10% Single Supply Voltage: Figure 1. Packages ■ Up to 4 Mbit of Primary Flash Memory 8 uniform sectors ■ 256Kbit Secondary Flash Memory (4 uniform

Contextual Info: PSD413F Family General Description The PSD4XX series of Field Programmable Microcontroller Peripherals represent a major advance in the evolution of Programmable Peripherals. They combine an innovative architecture with state of the art technology to provide user PROGRAMMABILITY

Contextual Info: PSD413F Family System Configuration The CSIOP signal, which is generated by the DPLD, selects the internal I/O devices or registers. The CSIOP signal takes up 256 bytes of address space and is defined by the user in the PSDSoft Software. The following is an address offset map for the various

D413a

Contextual Info: PSB413F Family Table 2. PSD413F Pin Descriptions The following table describes the pin names and pin functions of the PSD413F. Pins that have multiple names and/or functions are defined by user configuration. Pin Name ADIOO - ADI015 Pin Function Address/data bus

d413a

Contextual Info: PSD413F Family I/O Ports There are 5 program m able 8-bit I/O ports: Port A, Port B, Port C, Port D and Port E. These ports all have m ultiple operating m odes, depending on th e configuration. Som e of the basic functions are providing input/output fo r the ZPLD, or can be used for standard I/O. Each

Contextual Info: PSD413F Family Figure 33. Read Timing tAVLX _ tLXAX \ / - ALE/AS tLVLX A/D MULTIPLEXED BUS ADDRESS VALID DATA VALID tAVQV ADDRESS NON-MULTIPLEXED BUS \ r yz ADDRESS VALID DATA NON-MULTIPLEXED BUS & DATA VALID tSLQV tRLQV IRHQX «RLRH _RD PSEN, DS

T flip flop pin configuration

Contextual Info: PSD413F Family The PSD413A2F ZPLD Block Key Features □ 2 Embedded ZPLD devices □ 24 macrocells □ Combinatorial/registered outputs □ Maximum 126 product terms □ Programmable output polarity □ User configured register clear/preset □ User configured register clock input

National Semiconductor 8780 8 bit microcontroller

Abstract: Toshiba 8896 DSA0010131 hpc 3062 intel 80196 Introduction definitions intel 80196 microcontroller AMD 586 embedded PSD4135G2 HPC 932 transistor 0882
Contextual Info: Configurable Memory System on a Chip for 16-Bit Microcontrollers PSD4000 Series Product Brief PSD4135G2 PSD4235G2 April, 2000 Preliminary 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-TEAM-WSI 800-832-6974 Web Site: http://www.waferscale.com

ST 9427

Abstract: 80C51XA -G3 EEPROM ST 9422 80C164-80C167
Contextual Info: PSD4000 Series PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs November, 2000 Preliminary Information 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-832-6974 Web Site: http://www.psdst.com E-mail: ask.psd@st.com

Contextual Info: PSD413F Family AC/DC The following tables describe the AD/DC parameters of the PSD413F family: PSIiMNitBfS □ DC Electrical Specification □ AC Timing Specification • ZPLD Timing - Combinatorial Delays - Synchronous Clock Mode - Asynchronous Clock Mode

Contextual Info: PSD413F Family Power Management Unit The PSD413F provides many power saving options. By configuring the PMMRs Power Management Mode Registers , the user can reduce power consumption. Table 15 shows the bit configuration of the PMMRO and PMMR1. The microcontroller is able to

Contextual Info: PSD4135G2 PSD4135G2V Flash in-system programmable peripherals for 16-bit MCUs Features • Single supply volate – 3 V±10% PSD4135G2V – 5 V±10% (PSD4135G2) ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s

80C196 instruction set

Abstract: MC68331 PSD4000 PSD4135G2 TQFP80 80C51XA J1850 MC2001 683XX 68HC12
Contextual Info: PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs PRELIMINARY DATA FEATURES SUMMARY • 5 V±10% Single Supply Voltage: ■ Up to 4 Mbit of Primary Flash Memory 8 uniform sectors ■ 256Kbit Secondary Flash Memory (4 uniform sectors) ■

PSDPRO

Abstract: C167 boot AD10 AN1426 C167CR PSD4135G2 PSD4235G2 PSD4135 PSDsoft object file and third party programmers 0xDE00
Contextual Info: AN1426 APPLICATION NOTE Design Guide PSDsoft Express and PSD4135 CONTENTS • See next page January 2002 1/3 Contents 1 2 3 Introduction . 2

dk4000

Abstract: HPC 932 PSD4000 HATTELAND hpc 3062 386EX 683XX 68HC12 80386EX J1850
Contextual Info: Configurable Memory System on a Chip for 16-Bit Microcontrollers PSD4000 Series Product Brief PSD4135G2 PSD4235G2 April, 2000 Preliminary 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-TEAM-WSI 800-832-6974 Web Site: http://www.waferscale.com

intel 80296

Abstract: 80296 datasheet MCU-10 80C16x intel 80196 Introduction definitions HATTELAND 80C196NT Many-Time Programmable Flash PSD4000 68HC12
Contextual Info: PSD4000 Series PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs March, 2000 Beta Information 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-TEAM-WSI 800-832-6974 Web Site: http://www.waferscale.com E-mail: info@waferscale.com

pld decoder

Abstract: 683XX 68HC12 68HC16 80386EX 80C51XA C16X J1850 MC2001 PSD4000
Contextual Info: PSD4000 Series PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs November, 2000 Preliminary Information 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-832-6974 Web Site: http://www.psdst.com E-mail: ask.psd@st.com