PD302 Search Results

Contextual Info: STANLEY ELECTRIC CO LTD 5SE D • 4b7fll5ß QQ0201Ö 57b B I I S T ínlei -r¿+t- c2> PHOTODARLINGTON TRANSISTOR PD302 Package Dimensions ■ FEATURES • • • HIGH SENSITIVITY (lc = 12mW TYP. HIGH DIRECTIVITY MOLDED EPOXY TYPE ■ APPLICATION • •

PD302

Abstract: Rotary Encoder Interface
Contextual Info: A C INTERFACE INC 1QE D | 00233Û3 G O O C m ^ S | PD302 £1anlei r ^ i ^3 STANLEY PHOTO • Package Dimensions ■ FEATURES 1 High photocurrent i (Typ. 12mA at Ee = 0.01 mW/cm2) ] (2) High directivity *. (3) Low cost, long life time .di | ■ A P PLIC A TIO N S

PD302

Abstract: Stanley Electric
Contextual Info: STANLEY ELECTRIC CO LTD 55E D • 4b7fil5û SjÄKLEI GDD2Ü1Ô 57b M U S T 7 ^ -& 3 PHOTODARLINGTON TRANSISTOR_ PD302 Package Dimensions ■ FEATURES • • • HIGH SENSITIVITY lc = 12mW TYP. HIGH DIRECTIVITY MOLDED EPOXY TYPE ■ APPLICATION

PD3024

Abstract: la 1240 CFM024
Contextual Info: PACKAGE OUTLINES* PD3024 1.240 1.280 24 13 ID 1 12 i .240 290 -4 ♦ •*— .006 MIN. SEA TIN G P LA N E ■140 CD3024 1.235 1.280 .096 MAX. 290 *For reference only. 111 PACKAGE OUTLINES Cont'd. SO 024 .6141 ' .0926 — J i r u JL l l l : . : . : . : - L

Contextual Info: |j PD30200 VR4300 64-Bit Microprocessor NEC Electronics Inc. Addendum 1 January 1996 This addendum to the ^PD30200 D ata S h eet dated O ctober 1995 (Docum ent No. U 1 0 1 1 6 E J 1 V 0 D S 0 0 ) revises Section 8, Electrical C haracteristics, on p ages 42 and 43.

VR4320

Abstract: U10116E capacitor CTC1 ldr datasheet NEC VR4300
Contextual Info: PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT m PD30220 VR4320TM 64-BIT MICROPROCESSOR DESCRIPTION The m PD30220 VR4320 is a high-performance, 64-bit RISC (Reduced Instruction Set Computer) type microprocessor employing the RISC architecture developed by MIPS.

VR4300i

Contextual Info: NEC 8. ¿PD30200, 30210 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta = 25 °C Parameter Supply voltage Input voltageNote Symbol Condition V dd Vi Pulse of less than 10 ns Operating case temperature Storage temperature Note Tc Tstg The upper limit of the input voltage (V dd

gal programming algorithm

Abstract: PALCE29M16 PALCE29M16H PALCE29M16H-25 PD3024
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-25 Lattice Semiconductor PALCE29M16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • High-performance semicustom logic ■ Register/Latch Preload permits full logic replacement; Electrically Erasable EE

20V8Q

Abstract: SL06 20V8H-15 20V8 GAL20V8 PAL20R8 PALCE20V8 PD3024 pal20v8
Contextual Info: COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all PAL 20V8 devices ◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

sfe 5,5 ma

Abstract: CD3024 PD3024
Contextual Info: >rJ , J Am 29C?33/834 CMOS Parity Bus Transceivers PRELIMINARY > > 3 3 DISTINCTIVE CHARACTERISTICS • • • Low-power CMOS - ICC Static = 80 //A High-speed bidirectional bus transceiver for processor organized devices Error flag with open-collector output

CD3024

Abstract: PD3024 AM2S
Contextual Info: Am 29833A/834A - Am 29853A/854A Parity Bus Transceivers PRELIMINARY DISTINCTIVE CHARACTERISTICS High-speed bidirectional bus transceiver for processor organized devices Error flag with open-collector output Generates odd parity for all-zero protection Buffered direction three-state control

Am2963

Contextual Info: Am29833A/Am29853A/Am29855A Parity Bus Transceivers VSS86ZUJV/V8S86ZUIV/VSC86ZUIV DISTINCTIVE CHARACTERISTICS • High-speed bidirectional bus transceivers for processor organized devices - T-R delay = 6 ns typical - Rj-Parity delay = 9 ns typical • Error flag with open-collector output

PAL32VX10

Contextual Info: COM’L Advanced Micro Devices PAL32VX10/A 24-Pin Versatile with XOR Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Increased logic power ■ Global register asynchronous/synchronous preset/reset ■ Automatic register preset on power up ■ Preloadable output registers for testability

pal20ra10 mmi

Abstract: PAL20RA10
Contextual Info: COM’L : -20/std MIL: std Advanced Micro Devices PAL20RA10/-20 24-pin Asynchronous TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 20 ns maximum propagation delay and 30 MHz fMAx ■ Individually programmable asynchronous clock, preset, reset, and enable

Contextual Info: AmPALC29M Al 6 24-Pin E2-Based CMOS Programmable Array Logic ADVANCE INFORMATION Distinctive Characteristics • • • • • High-performance semi-custom logic replacement; Electrically Erasable E2 technology allows repro­ grammability 16 bidirectional user-programmable I/O logic macro­

Contextual Info: Am27S35/Am27S37 8,192-Bit 1024x8 Bipolar Registered PROM with Programmable INITIALIZE Input Versatile programmable asynchronous or synchronous enable for simplified word expansion Buffered common INITIALIZE input either asynchronous (Am27S35) or synchronous (Am27S37)

Contextual Info: COM’L PLS167-33, PLSCE167H-33 PLS168-33, PLSCE168H-33 Advanced Micro Devices 24-Pin TTL/CMOS Programmable Logic Sequencers DISTINCTIVE CHARACTERISTICS • ■ Field-programmable replacement for sequential control logic User-programmable pin for asynchronous

Contextual Info: Am29C827/Am29C828 Am29C927/Am29C928 Am29C827/Am29C828 Am29C927/Am29C928 High-Performance CMOS Bus Buffers DISTINCTIVE CHARACTERISTICS • • • High-speed CMOS buffers and inverters - D-Y delay = 7 ns typical Low standby power JEDEC FCT-compatible specs

Contextual Info: COM’L :-7/10/15 a MIL: -12/20 Advanced Micro Devices PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns propagation delay and 91 MHz fMAx external ■ 10 Macrocells programmable as registered or

TEA 2162 AE

Contextual Info: PR E LIM IN A R Y a COM’L Advanced Micro Devices PALCE20RA1 OH-15 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low power at 90 mA Ice ■ 15 ns maximum propagation delay and Programmable replacement for high-speed

Contextual Info: FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 PALCE20RA10 Family AduaM nlccero 24-Pin Asynchronous EE CMOS Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • ■ Low pow er at 100 m A Icc ■ TTL-level register preload for testability A s fast as 7.5 ns m axim um propagation delay

Am29C82

Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •

AMPAL22V10

Contextual Info: A m P A L 2 2 V 1 0-1 5 24-Pin IM O X III7“ Program m able Array Logic P R E L IM IN A R Y Distinctive Characteristics • • • • • • • • • 15-ns perform ance Increased logic pow er — up to 22 inputs and 10 outputs Increased product term s — average 12 per output

PLS105

Contextual Info: COM’L a PLS105-40, PLSCE105H-37 Advanced Micro Devices 28-Pin TTL/CMOS Programmable Logic Sequencer DISTINCTIVE CHARACTERISTICS • Field-programmable replacement for sequential control logic User-programmable pin for asynchronous flip-flop Preset/Output Enable