PD0005 Search Results

SO8w package outline

Abstract: SO16-150 SO8 Wide Package pd0005
Contextual Info: PD0005 Packing information Small Outline Packages for memory products Tape and Reel shipping media INTRODUCTION Surface-mount packages can be supplied with Tape and Reel packing. The reels are standard 330mm in diameter and contain between 1000 and 2500 devices. The packages

Contextual Info: TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SYNERG Y SY100S371 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 1000ps I e e min. of-68m A The SY100S371 is an ultra-fast triple 4-input multiplexer with true and complementary outputs designed for use in

35505-6000-B0MGF

Abstract: 35505-6000-B0M
Contextual Info: JNPS-0600 C, PD-0054 製品仕様書 Product Specification ３Ｍ 印 Power Clamp ﾜｲﾔｰﾏｳﾝﾄ ｿｹｯﾄ 35505-6XX0-X0X GF 3M Power Clamp Wire Mount Socket 35505-6XX0-X0X GF This document is a modified version of the original JNPS-0600C which is

Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs Companion chip to SY100S390 PECL-to-TTL translator Function and pinout compatible with National and Signetics F100K

Contextual Info: * QUINT EXCLUSIVE OR/NOR GATE SYNERGY SY100S307 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 1000ps The SY100S307 is an ultra-fast quint exclusive-O R / NOR gate designed for use in high-perform ance ECL system s. A function output that is the w ire-O R result of the

Contextual Info: * QUINT DIFFERENTIAL LINE RECEIVER SYNERGY SY100S314 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 900ps Differential outputs Iee min. o f-60 m A Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for

Contextual Info: * TRIPLE 2-WIDE OA/OAI GATE SYNERGY SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 900ps Iee min. o f-48 m A Extended supply voltage option: V ee = -4.2V to -5.5V The S Y 100S 317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed for use in high-perform ance ECL

Contextual Info: * TRIPLE 2-WIDE OA/OAI GATE SYNERGY SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed fo r use in high-perform ance ECL system s. This device offers both true and com plem ent outputs. The inputs on this device have 75K£2 pull-down

Contextual Info: * Q UAD DRIVER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 800ps Enable to Output max. of 950ps Iee SY100S313 min. o f-60 m A Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity

A03414

Abstract: package marking ae marking alpha omega
Contextual Info: Document No. K n rJ ALPHA & OMEGA SEMICONDUCTOR Version G Title A 03414 Marking Description SOT-23 PACKAGE MARKING DESCRIPTION NOTE: P - Package and product type N - Last digital of product number W - Week code A - Assembly location code L&T - Assembly lot code

A6 marking

Abstract: marking a6 sot23 marking code A6 sot23 03406 A6 MARKING CODE SOT23 marking alpha omega a6 marking code sot A03406
Contextual Info: Document No. K n rJ ALPHA & OMEGA SEMICONDUCTOR Version G Title A 03406 Marking Description SOT-23 PACKAGE MARKING DESCRIPTION NOTE: P - Package and product type N - Last digital of product number W - Week code A - Assembly location code L&T - Assembly lot code

Contextual Info: * QUINT EXCLUSIVE OR/NOR GATE SYNERGY SY100S307 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 1000ps The SY100S307 is an ultra-fast quint exclusive-O R / NOR gate designed for use in high-perform ance ECL system s. A function output that is the w ire-O R result of the

A03413

Contextual Info: Document No. K n rJ ALPHA & OMEGA SEMICONDUCTOR Version G Title A 03413 Marking Description SOT-23 PACKAGE MARKING DESCRIPTION NOTE: P - Package and product type N - Last digital of product number W - Week code A - Assembly location code L&T - Assembly lot code

Contextual Info: LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERG Y SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 3.7ns Iee min. o f-37 m A TTL outputs Extended supply voltage option: V ee = -4 .2 V to -5 .5 V 25% faster than National's 325 Differential inputs with built-in offset

DI 437 EB

Contextual Info: * HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps I e e min. o f-9 8m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V

Contextual Info: * SYNERGY SEMICONDUCTOR 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE FEATURES DESCRIPTION Max. propagation delay of 800ps Iee SY100S318 The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/ AND gate with both true and complementary outputs, designed for use in high-performance ECL systems. The

Contextual Info: SYNERG Y SY10422-3/4/5/7 SY100422-3/4/5/7 SY101422-3/4/5/7 SY101M422-5/7 2 56 X 4 E C L R A M SEMICONDUCTOR DESCRIPTION FEATURES • Address access time, tAA: 3/4/5/7ns max. The Synergy SY10/100/101422 are 1024-bit Random Access Memories RAMs , designed with advanced Emitter