PAL20 Search Results

Contextual Info: PAL20L8A, PAL20R4A, PAL20R6A, PAL20R8A STANDARD HIGH-SPEED PAL CIRCUITS D 2 7 0 6 , DEC EM BE R 1 9 8 2 - R E V IS E D DEC EM BE R 1 9 8 7 PAL20L8' M SUFFIX . . . JW PACKAGE C SUFFIX . . . JW OR NT PACKAGE Standard High Speed 25 ns PAL Family • Choice of Input/Output Configuration

pal20ra10 mmi

Abstract: PAL20RA10
Contextual Info: COM’L : -20/std MIL: std Advanced Micro Devices PAL20RA10/-20 24-pin Asynchronous TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 20 ns maximum propagation delay and 30 MHz fMAx ■ Individually programmable asynchronous clock, preset, reset, and enable

amd 20l10

Abstract: CED registers
Contextual Info: 24-Pin Enhanced Am PAL20RP10 Fam ily 24-Pin IMOX Programmable Array Logic PAL Elements D is tin c tiv e C h a ra c te ris tic s • • • • • • • PRELOAD feature permits full logical verification Reliability assured through more than 70 billion fuse

PAL20RA10-20

Contextual Info: Asynchronous PAL20RA10 Ordering Information Features/ Benefits • Programmable clock for asynchronous operation PAL20RA10-20 C NS STD • Programmable asynchronous set and reset • Programmable polarity PROGRAMMABLE ARRAY LOGIC XTTTTT1 • Local and global output enable control

PAL20

Abstract: PAL16L8A
Contextual Info: PAL 20 Series 16L8/16R8 16R6/16R4 CYPRESS SEMICONDUCTOR — 4.5-ns, Industry-Standard PLDs Features Functional Description • Ultra high speed supports today’s and tomorrow’s fastest microprocessors C ypress PAL20 Series devices consist of th e PAL16L8, PAL16R8, PAL16R6, and

PAL20L2

Contextual Info: PAL20L2 199- - Series 24 ma. M rtl_! '’ j STD FC Vcc : P in 24 C.ND : Pm 12 v ;v i . i i f l »/. H t i; N & MOT PAL N S * h RAY RCA S IC. TI £ SGS ;LIJ AMI) AMPAL CYPRESS CYPAL H ARRIS HPL LATTICE HAL M MI PAL ij 3 - * A A 2 A4 B B2 C

PAL20L8

Abstract: MMI PAL 20R4 mmi pal20l8 PAL20R4 MMI TOP MARKING amd part marking PAL20R6 PAL20L8 mmi AMD PAL20L8 LA4490
Contextual Info: COM’L: -5/7/B/B-2/A, 10/2 a MIL: -10/12/15/B/A Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic D ISTINCTIVE CHARACTERISTICS • As fast as 5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8,20R8,

PAL20R4

Contextual Info: — 210 — PAL20R4 Series 24 A g « ~h fi ¡ii X nput feedback tpd enable clock X / max clock L max min STD A A2 B A4 D 7 10 7 .5 40 10 10 ns 40 10 8 ns B2 max 25 40 max 25 max 20 « . ns max 15 20 7 .5 6 .5 ns min 2 8 .5 18.1 6 0 .6 74 MHz min 15 15 7

PAL20X4ACNS

Abstract: palasm PAL20X10 MMI PAL20L10 MMI pal20x4a
Contextual Info: COM’L: A/B/-20/AL MIL: A PAL20X10A Series PAL20L10B/-20/AL Advanced Micro Devices XOR Registered 24-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • XOR gates on registered outputs Register preload for testability ■ Efficient implementation of counters

mmi pal20l8

Abstract: pal20l8 PAL20R4-7PC PAL20R8B PAL20R8 Family february 1996
Contextual Info: FINAL COM’L: -5/7/B/B-2/A, 10/2 H Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 5-ns propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8,20R8, 20R6, 20R4

PAL20S10

Abstract: PAL20RS10 20S10 20RS10 PAL20RS4 PAL20RS8 20RS8 pal20s
Contextual Info: Large 24RS Series 20S10, 20RS10, 20RS8, 20RS4 Large 24RS Series OUTPUTS STANDARD ARRAY INPUTS PAL20S10 PAL20RS10 PAL20RS8 PAL20RS4 COMBINATORIAL REGISTERED tpo* ns Ice (m A) 10 2 6 10 8 4 35/40 35 35/40 35/40 240 240 240 240 20 20 20 20 *35ns active low, 40ns active high

PAL16RA8

Abstract: PAL20RA10 20RA
Contextual Info: L a rg e 2 0 R A S e rie s 16RA8 Large 20RA PAL16RA8 Description Programmable Polarity The PAL16RA8 is a 20-pin registered asynchronous PAL device. It is a 20-pin version of the original asynchronous PAL device, the PAL20RA10. This versatile device features pro­

20l8

Abstract: 20l8a-2 20L8A PAL20L8 PAL20R4 PAL20R6 PAL20R8 ZPAL24 20R4A Monolithic Memories PAL20L8
Contextual Info: M edium 2 4 S e rie s 20L8, 20R8, 20R6, 20R 4 Medium 24 Series O U TPU TS D E D IC A TE D IN PU TS 12 10 10 10 P AL20L8 PAL20R 8 PAL20R 6 PAL20R 4 S uffix *PD ns Ice <mA) A A-2 B B-2 * 25 35 15 25 210 105 210 105 * co n ta c t M o no lith ic M em ories fo r d ata she e t

AMD am3 socket pinout

Abstract: amd socket am3 pinout AMD 140 Socket AM3 amd pinout diagram socket AM3 MR 4710 AMD Socket AM3 amd AM3 PIN LAYOUT MR 4710 IC OO3A MARKING AMD socket AM3 pin diagram
Contextual Info: ADV MI CRO PLA/PLE/ARRAYS COM’L SÛE 02S7S2b D 0 0 8 =1 4 4 3 3 B A MDS MIL E T—46— 19-13 Advanced Micro Devices PAL20R8 Family 24-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns maximum propagation delay Easy design w ith PALASM softw are

pal20ra10

Contextual Info: PAL20RA10 ZWÂ National Æià Semiconductor PAL20RA10 Programmable Array Logic PAL General Description The PAL20RA10 is a new member of National’s broad PAL family. It provides several new features which will dramati­ cally benefit PAL users. National Semiconductor’s ad­

Contextual Info: COM’L : -20/std MIL: std PAL20RA10/-20 Advanced Micro Devices 24-pin Asynchronous TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 20 ns maximum propagation delay and 30 MHz I max ■ Individually programmable asynchronous clock, preset, reset, and enable

palc20r

Contextual Info: PAL20R8 Family 20L8, 20R8 20R6, 20R4 F e a tu re s /B e n e fits P erfo rm an ce • Standard 24-pin architectures Several sp ee d /p o w e r versions are available. • TTL and CMOS versions • High speed, as fast as 15 ns tPD lor PAL20R8B Series • Low power, as low as zero standby for PALC20R8Z Series

PAL20L10 MMI

Abstract: pal 007a PAL20X10 MMI PAL20X10 AMD part numbering DIAGRAM pal 005a pal 010a PAL20X8A odv marking pal 005a
Contextual Info: COM’L: A/B/-20/AL MIL: A a Advanced Micro Devices PAL20X10A Series PAL20L10B/-20/AL XOR Registered 24-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • XOR gates on registered outputs Register preload for testability ■ Efficient Implementation of counters

MAX3520

Contextual Info: — 202 — PAL20X1O Series 24 JH tl A g t} iU z enable tpd X clock / m ax tw clock L H tsu thold - input feedback Vcc-M A X Icc II H L Io — «- - - max A A2 45 20 35 ns max 35 20 25 ns A4 B B2 30 15 25 ns min 12.5 22.2 16 MHz ns min 35 25 25 min 25 1.5

Contextual Info: PAL20X1OA Series 20L1OA, 2 0 X 1 OA 20X 8A , 20 X 4A Ordering Information F eatures/ Benefits • XOR gates on registered outputs PAL20X10A C NS STD • Efficient implementation of counters ~ n PR O G R A M M A B LE ARRAY L O G IC • Register preload • Power-up reset

PAL20RS10

Contextual Info: PA L20R S 10 Series 20S 10 , 20R S10 20 R S 8, 2 0 R S 4 Features/ Benefits Ordering Information • Product term steering allows up to 16 product terms per output PAL20RS10 C NS STD PROGRAMMABLE ARRAY LOGIC • Programmable polarity □ T T T 1 PROCESSING

20RA10

Abstract: PAL20RA10
Contextual Info: Lars« 2 4 R A 20RA10 Large 24RA PAL20RA10 Description Programmable Polarity The PAL20RA10 is a 24-pin registered asynchronous PAL device. This versatile device features programmable clock, enable, set, and reset, all of which can operate asynchronous­

Monolithic Memories PAL20L8

Abstract: 20L8A
Contextual Info: M ed iu m 2 4 S e rie s 20L8, 20R8, 20R6, 20R 4 Medium 24 Series OUTPUTS DEDICATED INPUTS COMBINATORIAL PAL20L8 PAL20R8 P A L20R 6 PAL20R4 12 10 10 10 REGISTERED 8 6 4 8 6 I/O 2 I/O 4 I/O Description The Medium 24 Series consists of four devices, each with

Contextual Info: Medium 2 4 X Series 2 0 L1 0 , 2 0 X 1 0 , 2 0 X 8 , 2 0 X 4 Medium 24X Series STANDARD OUTPUTS ARRAY INPUTS PAL20L10 PAL20X10 PAL20X8 PAL20X4 20 20 20 20 COMBINATORIAL REGISTERED 10 2 10 8 4 6 ns •cc (mA) (ns) Ice (mA) 50 50 50 50 165 180 180 180 30 30