P3S12D40ETP Search Results

P3S12D40ETP

Abstract: No abstract text available
Text: 512Mb DDR Synchronous DRAM P3S12D30/40ETP DESCRIPTION P3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, P3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output