N74F109D-T Search Results
N74F109D-T Result Highlights (2)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| SN74F109DR |
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Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
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| SN74F109D |
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Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 |
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N74F109D-T Datasheets (2)
| Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | |
|---|---|---|---|---|---|---|
| N74F109D-T |
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Positive J-Knot positive edge-triggered flip-flops - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 125 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: -1/+20 mA ; Propagation delay: 6.2 ns; Voltage: 4.5-5.5 V | Original | |||
| N74F109D-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical |