LVEP210 Search Results

LVEP111

Abstract: 220 to 110 MC100LVEP111FA ARD900/D
Contextual Info: ARD900/D Rev. 0, Oct-2000 Clock or Data Distribution Devices New devices— Introducing Low Voltage ECLinPS Plus Line LVEP. Delivering Faster Operation and Finer Edge Placement EP11 EPT 23 LVTTL or LVCMOS EPT 23 LVTTL or LVCMOS B A LVEP210 / LVEP111 /

LVEP210

Abstract: MC100 MC100EP210 MC100LVEP210
Contextual Info: LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

Contextual Info: LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

Contextual Info: LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The

vbb vcc vee

Contextual Info: LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

NTP4N60

Abstract: 8051 based thyristor firing circuit power MOSFET IRF740 driver circuit Curtis 1178 MAX766 8051 microcontroller Thyristor firing circuit ATX smps from 12 volt irf740 Intel ATX smps circuit diagram desktop computer smps circuit diagram
Contextual Info: Q U A R T E R L Y T E C H N O L O G Y A N D A P P L I C AT I O N S M A G A Z I N E ON-Display THIRD QUARTER 2000 Vol. 1, No. 1 This Quarter. FEATURES ON Semiconductor Adds Cherry Semiconductor 3 Control Scheme Gives Power Tune-Up 15 A P P L I C AT I O N S

k1117

Abstract: R36W power transistor k1821 L46R k1518 k1117 transistor k2225 transistor k2225 k1317 transistor k1317
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS

KLT20

Abstract: k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139
Contextual Info: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and

Contextual Info: LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is

motorola HEP cross reference

Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
Contextual Info: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.

LVEP210

Abstract: MC100 MC100EP210 MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2
Contextual Info: LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is

Contextual Info: CDCLVP215 www.ti.com SCAS853B – APRIL 2008 – REVISED NOVEMBER 2009 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL CLOCK DRIVER Check for Samples: CDCLVP215 FEATURES 1 • • • • APPLICATIONS • • QA3 QA4 QA4 QB0 QB0 QB1 QB1 QA3 24 23 22 21 20 19 18 17

CDCLVP215

Abstract: CDCLVP215RHBR LVEP111 LVEP210 MC100 QFN32 SCAA056 B41012
Contextual Info: CDCLVP215 www.ti.com. SCAS853A – APRIL 2008 – REVISED OCTOBER 2008 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL

R36W

Abstract: k1420 N52C N38C l46r k0114 N53C transistor k1117 k2225 transistor transistors k2628
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information

LVEP210

Abstract: m 1305 MC100 MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2
Contextual Info: LVEP210 Low-Voltage 1:5 Dual Diff. LVECL/LVPECL/LVEPECL/HSTL Clock Driver The LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The LVECL/LVPECL input signals can be either differential or single–ended if the VBB output is

Contextual Info: LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The

transistor r1010

Abstract: 555N pw-3n BF 245 A spice BF172 MJE 280 power transistor TT2120 BF192 transistor r1011 transistor D113
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective Schematic Information The objective of ”AND8009 ECLinPS Plus SPICE Modeling Kit” is to provide sufficient circuit schematic and

MC100LVEP210FAR2

Abstract: LVEP210 MC100 MC100EP210 MC100LVEP210 MC100LVEP210FA
Contextual Info: LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The

k1213

Abstract: k1118 transistor k1317 k1117 K2225 k2225 transistor k0305 K0319 c1213 transistor k1117 transistor
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information

CDCLVP215

Abstract: CDCLVP215RHBR LVEP111 LVEP210 MC100 QFN32 SCAA056
Contextual Info: CDCLVP215 www.ti.com. SCAS853A – APRIL 2008 – REVISED OCTOBER 2008 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL

Contextual Info: LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

Contextual Info: CDCLVP215 www.ti.com SCAS853B – APRIL 2008 – REVISED NOVEMBER 2009 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL CLOCK DRIVER Check for Samples: CDCLVP215 FEATURES 1 • • • • APPLICATIONS • • QA3 QA4 QA4 QB0 QB0 QB1 QB1 QA3 24 23 22 21 20 19 18 17

Contextual Info: CDCLVP215 www.ti.com SCAS853B – APRIL 2008 – REVISED NOVEMBER 2009 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL CLOCK DRIVER Check for Samples: CDCLVP215 FEATURES 1 • • • • APPLICATIONS • • QA3 QA4 QA4 QB0 QB0 QB1 QB1 QA3 24 23 22 21 20 19 18 17

k2324

Abstract: k1821 k2225 k1317 power transistor k1821 k1213 k1117 k0313 k2225 transistor N13R
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS