IDT29FCT521 Search Results

DSC4002

Abstract: S-1047 29FCT520A S1047
Contextual Info: I N T E G R A T E » D E VI CE » • ^aas77i o D o m o a MULTILEVEL PIPELINE REGISTERS 2 PRELIMINARY IDT 29FCT520A/B IDT 29FCT521A/B ~T-L/ 6 -0 9 -0 *1 FEATURES: DESCRIPTION: • The IDT29FCT520A/B and IDT29FCT521A/B each contain four 8-blt positive edge-triggered registers. These may be operated as

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. DESCRIPTION: FEATURES: • • • • • • • • • A, B, C and D speed grades Low input and output leakage <1 [iA max. CMOS power levels

FCT520

Abstract: IDT29FCT521AT SO24-2
Contextual Info: IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT MULTILEVEL PIPELINE REGISTERS Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/ BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Fastest CMOS logic family available • A, B, C and D speed grades with 5.2ns tPD • Available in DIP, SOIC, SSOP, CERPACK and LCC

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. DESCRIPTION: FEATURES: Th e ID T 2 9F C T 520 A T /B T /C T /D T and ID T 2 9F C T 521 A T / B T /C T /D T each contain four 8-bit positive edge-triggered

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29 FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc* FEATURES: DESCRIPTION: • • • • The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/ BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT FEATURES: DESCRIPTION: • • • • The IDT29FCT520AT/BT/CT/DT and IDT29FCT521 AT/ BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a

T520C

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT FEATURES: DESCRIPTION: • • • • The IDT29FCT520AT/BT/CT/DT and IDT29FCT521AT/ BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • • The 1DT29FCT520AT/BT/CT/DT and IDT29FCT521AT/ BT/CT/DT each contain four 8-bit positive edge-triggered registers. These may be operated as a dual 2-level or as a

L29C521

Abstract: Y5916
Contextual Info: L29C520/521 L29C520/521 DEVICES INCORPORATED 4 x 8-bit Multilevel Pipeline Register 4 x 8-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 8-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register

Contextual Info: LPR520/521 LPR520/521 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline

Contextual Info: d t M ULTILEVEL PIPELINE REGISTERS IDT29FCT520A/B !D T 29FC T521A / b FEATURES: DESCRIPTION: • Equivalent to AMD’s Am29520/21 bipolar Multilevel Pipeline Registers in pinout/function, speeds and output drive over full temperature and voltage supply extremes

L29C521PC-1

Contextual Info: L29C520/521 4 x 8-bit Multilevel Pipeline Register FEATURES DESCRIPTION □ Fou r 8-bit R egisters □ Im plem ents D ouble 2-Stage Pipe­ line or Sin g le 4-Stage P ipeline Register □ H old, Shift, and Load Instructions □ Separate D ata In and D ata O ut Pins

Contextual Info: S mr •■ S S ' L29C520/521 — 4 x 8-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION □ Four 8-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, and Load Instructions

IDT29FCT520

Contextual Info: L29C520/521 □ FV IC E S IN C O R P Q R A T F D DESCRIPTION FEATURES □ Four 8-bit Registers □ Im plem ents Double 2-Stage Pip e­ line or Single 4-Stage Pipeline Register □ H old, Shift, and Load Instructions □ Separate D ata In and Data O ut Pins

P174FCT244

Abstract: P174LPT-245 P174FCT574T P174FCT245T P174LPT QS74FCT280 P174FCT24 P174LPT16373 IDT74FCT IDT74FBT2827
Contextual Info: fl PERICOM I I I I I I II II I I I I I I I II I I I I I I I I II I I I I I II I I I I I I I I I I I II I M I I I I II I I I I I I I I I I I I I I II I I I I II I I I I I I I I I I I I I I I I I I I I I I I I I I | 1 I I | II PRODUCT CROSS REFERENCE GUIDE

61772

Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-OA APPROVED REV SHEET REV SHEET REV STATUS OF SHEETS REV SHEET PMIC N/A STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE A M S C N/A 1 2 3 4

Contextual Info: L29C520/521 D f-V lO tS INCORPORATED DESCRIPTION FEATURES □ Fou r 8-bit R egisters □ Im plem ents D ouble 2-Stage Pipe­ line or Sin g le 4-Stag e P ipeline Register □ H old, Shift, and L oad Instructions □ Separate D ata In and D ata O ut Pins □ H igh-Speed, Low P ow er C M O S

SMD M1 DIOD

Contextual Info: — “ “ L29C520/521 — 4 x 8 -bit M u lt ile v e l P i p e l i n e R e g is t e r F E A T U R E S D E S d t r n o N □ Four 8-bit Registers □ Im plem ents Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ H old, Shift, and Load Instructions

Contextual Info: LPR520/521 4 x 16-bit Multilevel Pipeline Register DESCRIPTION FEATURES □ Four 16-bit R egisters □ Im plem ents D ouble 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ H old, Shift, and L oad Instructions □ Separate D ata In an d D ata O ut Pins

Contextual Info: L29C520/521 D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ Four 8-bit Registers □ Im plem ents Double 2-Stage Pip e­ line or Single 4-Stage Pipeline Register □ H old, Shift, and Load Instructions □ Separate D ata In and Data O ut Pins

Contextual Info: LPR520/521 4 x 16-bit Multilevel Pipeline Register V IC I S INCORPORA ILL DESCRIPTION FEATURES □ Four 16-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, and Load Instructions □ Separate Data In and Data Out Pins

Contextual Info: L29C520/521 4 x 8-bit Multilevel Pipeline Register D E V IC E S IN C O R P O R A T E D I DESCRIPTION FEATURES □ Four 8-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, and Load Instructions □ Separate Data In and Data Out Pins

L29C520

Abstract: L29C520JC14 L29C520JC22 L29C520PC14 L29C520PC22 AM29520 smd diode y4
Contextual Info: L29C520/521 L29C520/521 DEVICES INCORPORATED 4 x 8-bit Multilevel Pipeline Register 4 x 8-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 8-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline