ICS93727 Search Results

ICS93727 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
ICS93727		Integrated Circuit Systems	DDR Phase Lock Loop Zero Delay Clock Buffer		Original	PDF

ICS93727 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Rstep protocol Contextual Info: ICS93727 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Zero Delay Clock Buffer patent pending Recommended Application: DDR Zero Delay Clock Buffer GND DDRC0 DDRT0 VDD DDRT1 DDRC1 GND GND DDRC2 DDRT2 VDD SCLK CLK_IN GND	Original	ICS93727 66MHz) 120ps 100MHz) 100ps 450ps 950ps Rstep protocol	PDF
Rstep protocol Abstract: rstep 0711B r-step Contextual Info: ICS93727 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Zero Delay Clock Buffer patent pending Recommended Application: DDR Zero Delay Clock Buffer GND DDRC0 DDRT0 VDD DDRT1 DDRC1 GND GND DDRC2 DDRT2 VDD SCLK CLK_IN *FS_PROG0	Original	ICS93727 66MHz) 120ps 100MHz) 100ps 450ps 950ps Rstep protocol rstep 0711B r-step	PDF
r-step Abstract: Rstep protocol ICS93727 rstep Contextual Info: ICS93727 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Zero Delay Clock Buffer patent pending Recommended Application: DDR Zero Delay Clock Buffer GND DDRC0 DDRT0 VDD2.5 DDRT1 DDRC1 GND GND DDRC2 DDRT2 VDD2.5 SCLK CLK_IN	Original	ICS93727 66MHz) 120ps 100MHz) ICS93727yF-T 0711B--10/10/02 r-step Rstep protocol ICS93727 rstep	PDF

Catalog Datasheet

Type

Document Tags

PDF

Rstep protocol

Contextual Info: ICS93727 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Zero Delay Clock Buffer patent pending Recommended Application: DDR Zero Delay Clock Buffer GND DDRC0 DDRT0 VDD DDRT1 DDRC1 GND GND DDRC2 DDRT2 VDD SCLK CLK_IN GND

Original

ICS93727 66MHz) 120ps 100MHz) 100ps 450ps 950ps Rstep protocol

PDF

Rstep protocol

Abstract: rstep 0711B r-step
Contextual Info: ICS93727 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Zero Delay Clock Buffer patent pending Recommended Application: DDR Zero Delay Clock Buffer GND DDRC0 DDRT0 VDD DDRT1 DDRC1 GND GND DDRC2 DDRT2 VDD SCLK CLK_IN *FS_PROG0

Original

ICS93727 66MHz) 120ps 100MHz) 100ps 450ps 950ps Rstep protocol rstep 0711B r-step

PDF

r-step

Abstract: Rstep protocol ICS93727 rstep
Contextual Info: ICS93727 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Zero Delay Clock Buffer patent pending Recommended Application: DDR Zero Delay Clock Buffer GND DDRC0 DDRT0 VDD2.5 DDRT1 DDRC1 GND GND DDRC2 DDRT2 VDD2.5 SCLK CLK_IN

Original

ICS93727 66MHz) 120ps 100MHz) ICS93727yF-T 0711B--10/10/02 r-step Rstep protocol ICS93727 rstep

PDF