Untitled
Abstract: No abstract text available
Text: HD74HC113 Dual J-K Flip-Flops with Preset REJ03D0563-0200 (Previous ADE-205-436) Rev.2.00 Oct 11, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and
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HD74HC113
REJ03D0563-0200
ADE-205-436)
HD74HC113P
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Hitachi DSA00279
Abstract: No abstract text available
Text: HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)
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HD74HC11
Hitachi DSA00279
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PDF
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Hitachi DSA00279
Abstract: No abstract text available
Text: HD74HC113 Dual J-K Flip-Flops with Preset Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is
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HD74HC113
Hitachi DSA00279
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PDF
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HD74HC11FPEL
Abstract: HD74HC11 sem 2005 SOP14 package HD74HC11P HD74HC11RPEL PRDP0014AB-B PRSP0014DF-B
Text: HD74HC11 Triple 3-input AND Gates REJ03D0539-0200 Previous ADE-205-411 Rev.2.00 Oct 06, 2005 Features • • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V
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HD74HC11
REJ03D0539-0200
ADE-205-411)
PRDP0014AB-B
DP-14AV)
HD74HC11P
DILP-14
HD74HC11FPEL
OP-14
HD74HC11RPEL
HD74HC11FPEL
HD74HC11
sem 2005
SOP14 package
HD74HC11P
HD74HC11RPEL
PRDP0014AB-B
PRSP0014DF-B
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PDF
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HD74HC11
Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN 2054.11
Text: HD74HC11 Triple 3-input AND Gates ADE-205-411 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max
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Original
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HD74HC11
ADE-205-411
HD74HC11
Hitachi DSA0095
DP-14
FP-14DA
FP-14DN
2054.11
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PDF
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HD74HC112
Abstract: PRSP0016DH-B HD74HC112FPEL HD74HC112P PRDP0016AE-B
Text: HD74HC112 Dual J-K Flip-Flops with Preset and Clear REJ03D0562-0200 (Previous ADE-205-435) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of
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Original
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HD74HC112
REJ03D0562-0200
ADE-205-435)
HD74HC112
PRSP0016DH-B
HD74HC112FPEL
HD74HC112P
PRDP0016AE-B
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PDF
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Hitachi DSA00279
Abstract: No abstract text available
Text: HD74HC114 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops
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Original
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HD74HC114
Hitachi DSA00279
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PDF
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Hitachi DSA00279
Abstract: No abstract text available
Text: HD74HC112 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.
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HD74HC112
Hitachi DSA00279
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PDF
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FP-14DN
Abstract: HD74HC113 DP-14 FP-14DA Hitachi DSA003765
Text: HD74HC113 Dual J-K Flip-Flops with Preset Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is
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HD74HC113
FP-14DN
HD74HC113
DP-14
FP-14DA
Hitachi DSA003765
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PDF
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HD74HC112
Abstract: Hitachi DSA003739
Text: HD74HC112 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear
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HD74HC112
HD74HC112
Hitachi DSA003739
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PDF
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DP-14
Abstract: FP-14DA FP-14DN HD74HC11 Hitachi DSA00333
Text: HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)
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Original
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HD74HC11
DP-14
FP-14DA
FP-14DN
HD74HC11
Hitachi DSA00333
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PDF
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DP-14
Abstract: FP-14DA FP-14DN HD74HC114 Hitachi DSA00334
Text: HD74HC114 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops are
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Original
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HD74HC114
DP-14
FP-14DA
FP-14DN
HD74HC114
Hitachi DSA00334
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC114 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock T h u flip-flop it edge sensitive to the clock input and change PIN ARRANGMENT state on the negative transition of the dock pulse. Each flipflop hai independant J, K, and preset inputs and Q and Q
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HD74HC114
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PDF
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74HC114
Abstract: No abstract text available
Text: HD74HC114 D u al J-K F lip -F lo p s with Preset, Common Clear, and Common Clock This flip-flop is edge sensitive to the clock input and change PIN ARRANGMENT state on the negative transition of the clock pulse. Each flipflop has independent J, K, and preset inputs and Q and Q
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OCR Scan
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HD74HC114
74HC114
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PDF
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/NEM *Ì2~ " ¿ E l 4 4 ^ 3 0 3 □ □ l G 3 b [ì S 92D HD74HC112 # Dual J-K Flip-Flops Each flip -flo p has independent J, K , preset, clear, and clock 10369 T - % - D “7-07 w ith P re s e t and C le a r | PIN ARRANGEMENT inputs and Q and Q outputs. This device is edge sensitive to
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OCR Scan
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HD74HC112
0D1D315
T-90-20
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC113 # Dual J-K Flip-Flops i-vith Preset • PIN ARRANGMENT This flip-flop ii edge sensitive to the dock input and change state on the negative going transition of the dock pulse. Each \~ J~ ~ one has independent v, K, dock, and preset inputs and Q -«nd
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OCR Scan
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HD74HC113
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PDF
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/MEd ^5 T>Ë| i t i n t 2 0 3 0Q10330 Q 92D HD74HC11 # 103 30 D TVV 3 ' 2 / Triple 3-input AND Gates • F E A T UR E S I PIN ARRANGEMENT • High Speed Operation: tpcj= 9ns typ. C/_=50pF • High O u tptt Current: Fanout of 10 LSTTL Loads
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OCR Scan
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0Q10330
HD74HC11
0D1D315
T-90-20
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PDF
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Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/AR RAYS/MEM =IS DË1 4 ln t a 0 3 0010371 3 | 92D HD74HC113 10371 D T -q o -O”7 -07 Dual J-K Flip-Flops (with Preset This flip-flop is edge sensitive to the clock input end change | PIN ARRANGMENT state on the negative going transition of the clock pulse. Each
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OCR Scan
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HD74HC113
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC112 • Dual J K Flip-Flops with P reset and Clear Each flip-flop has independent J, K, preset, clear, and clock • PIN ARRANGEMENT input» and Q and Q outputs. This device is edge sensitive to the d o c k input and change state on the negative going transi
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OCR Scan
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HD74HC112
Ta-25
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC112 Each flip -flo p has independent J, K, # Dual J-K Flip-Flops w ith P re s e t and C le a r preset, clear, and clock | PIN ARRANGEMENT inputs and Q and Q outputs. This device is edge sensitive to the clock in put and change state on the negative going transi
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OCR Scan
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HD74HC112
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC11 # Triple 3-input AND Gates I PIN A R R A N G EM EN T • FEATURES • Hiflri Speed Operation: tp<j m 9ns typ. Q_ “ 5 0 p F I • Higii O utp ut C u rre n t: Fanout o f 10 L S T T L Load* • Wide Operating Voltage: V c c « 2 ~ 6 V • L o w Inp u t Current: 1 p A max.
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OCR Scan
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HD74HC11
To-25
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC11 # Triple 3-input AND Gates • FEATURES I PIN ARRANGEMENT • High Speed Operation: tpcj = 9ns ty p . C/_ = 5 0 p F • High O u tp u t C urrent: Fanout o f 10 L S T T L Loads • Wide Operating Voltage: Vcc = 2 ~ 6 V • Low In p u t C urrent: 1/uA max.
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OCR Scan
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HD74HC11
20jjA
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PDF
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HC125
Abstract: HC126 HD74HC128 HC-126 HD74HC1125 HD74HC126
Text: HD74HC1125, HD74HC12 6 * S Ä Ä * The HD74HC125, HD74HC128 faquir* the 3-«ta«e control input C to be taken high to put the output into the high Im pedance condition, whereat the HD74HC125, HD74HC126 requires the control input to be low to put the output into
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HD74HC1125,
HD74HC12
HD74HC125,
HD74HC128
HD74HC126
HC125
HC126
HC125
HC126
HC-126
HD74HC1125
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PDF
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Untitled
Abstract: No abstract text available
Text: HD74HC11 # Triple 3 -input AND Gates PIN ARRANGEMENT • FEATURES • • • • • High Speed Operation: tpdm9ns typ. C/_ *50pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: Vcc = 2 ~ 6 V Low Input Current: 1/uA max. Low Quiescent Supply Current:/cc (static) = 1>iA max. (7a> 25°C)
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OCR Scan
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HD74HC11
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PDF
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