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    SMPTE-292

    Abstract: ldc 2000 rev.01
    Text: HDTV 1.5 Gbit/s Re-timer GD14526 Preliminary General Information Features When in lock, the digital Lock Detect Circuit LDC uses the incoming data to control the PLL. When not in lock, i.e. the VCO frequency is more than 500 ppm away from the REFCK frequency, the


    Original     		PDF GD14526 GD14526 SMPTE292. DK-2740 SMPTE-292 ldc 2000 rev.01