FIN1018M Search Results

FIN1017

Abstract: FIN1018 FIN1018K8X FIN1018M FIN1018MX M08A MO-187
Contextual Info: Revised April 2002 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

FIN1017

Abstract: FIN1018 FIN1018K8X FIN1018M FIN1018MX M08A
Contextual Info: Revised September 2001 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

FIN1017

Abstract: FIN1018 FIN1018K8X FIN1018M FIN1018MX M08A
Contextual Info: Revised April 2001 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

IC LM7808 8V Voltage regulator

Abstract: tl494ch UC3525 application notes LM7915 to-3 lm7812 voltage regulator spec. sheet UC3525 LM7808 TO3 LM2951CM SG3524BN National Semiconductor voltage regulator lm7812
Contextual Info: Linear Products Cross Reference Guide Summer 2004 National Semiconductor provides a comprehensive set of support services. Product information, including sales literature and technical assistance is available through National's Customer Support Centers. Linear Products Cross Reference Guide – 2004

Contextual Info: Revised February 2002 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

Contextual Info: Preliminary Revised February 2001 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver Preliminary General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal

Contextual Info: Revised December 2001 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver General Description Features This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal