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    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 256M bits SDRAM EDS2532CABJ 8M words x 32 bits Description Pin Configurations The EDS2532CA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.


    Original     		PDF EDS2532CABJ EDS2532CA 90-ball 133MHz/100MHz M01E0107 E0460E30

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 256M bits SDRAM EDS2532CABJ 8M words x 32 bits Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V


    Original     		PDF EDS2532CABJ 90-ball 133MHz/100MHz cycles/64ms M01E0107 E0460E40

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 256M bits SDRAM EDS2532CABJ 8M words x 32 bits Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Clock frequency: 133MHz/100MHz (max.)


    Original     		PDF EDS2532CABJ 90-ball 133MHz/100MHz cycles/64ms M01E0107 E0460E40