ECL10 Search Results

D3351

Contextual Info: TIEPAL10H16TE6C TTL-TO-ECLIMPACT-X PAL TRANSLATOR CIRCUIT D3351. OCTOBER 1989 • ECL10H Programmable Logic with TTL-to-ECL Translation JT p a c k a g e TOP VIEW • ECL Control Inputs

pj 57

Abstract: 4914 CD 910 coax ECL10 SP10107
Contextual Info: SP10107 9 PLESSEY ECL10,000 SERIES SEMICONDUCTORS SP10107 T R IP L E 2-IN PU T E X C L U S IV E O R /E X C L U S IV E NOR P O S IT IV E LO G IC T h is three gate array is designed to provide the posi­ tive logic E xclu sive O R and E xclu sive N O R functions

Contextual Info: lowprofile ECL100K COMPATIBLE LOGIC DELAY MODULE # # # # # # ECL 100K in put and outputs Delays stable and precise 24-pin DIP package .375 high Available in delays fro m 16 to 80ns 12.5% taps — each isolated and w ith 70 ECL DC fan-out capacity Fast rise tim e on all outputs

Contextual Info: ECL100K COMPATIBLE 4-BIT RAMMABLE DELAY LINE ECL 100K input and output levels Delays stable and precise 24-pin DIP package .375 high The Available in delays up to 77.8ns Logic Delay Lines are digitally programmable by the presence of either a " 1 " or a " 0 " at each o f the programming

Contextual Info: ECL DIGITAL DELAY LINES RESISTORS •CAPS » COILS •DELAY U NES E10 SERIES - ECL10KINTERFACED E100 SERIES - ECL 100K INTERFACED FEATURES □ Industry’s widest selection! □ Economical cost, prompt delivery □ Fast 2nSec rise time typical □ Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

K1149

Abstract: 50-to-75 RASCO k1519 ECL10KH K1149BA K1149CA K1523BA K1524AA power supply 5v dc
Contextual Info: K1149 Series ECL Compatible Oscillators ECL10KH Based Design - provides im­ proved rise and fall times, duty cycle, noise margins and power supply rejection over the earlier 10K family while retaining compatibil­ ity. Open emitter output allows the user to

1N4148

Abstract: DS3643-1 ECL10K SP8647 GEC Plessey dg
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3643-1•2 SP8647 250MHz4 410/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high

DS3647-1

Abstract: ECL10K SP8690 SP8691 SP8690A
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3647-1•2 410/11 SP8690 200MHz4 48/9 SP8691 200MHz4 The SP8690 and SP8691 are low power ECL variable modulus dividers, with both ECL10K and TTL/CMOS compatible

Contextual Info: M MOTOROLA Military 10H509 Dual 4-5 Input “OR/NOR” Gate HP0 ELECTRICALLY TESTED PER: 5962-8985601 The 10H509 is a dual 4-5 input OR/NOR gate. This MECL1 OH part is afunction­ al/pinout duplication of the standard M ECL10K family part, with 100% improve­

Contextual Info: ECL10KH for High Performance System Design The designer of high-perform ancedigital system s now has new alternatives with the introduction o f M onolithic M em ories’ E C L 10KH fam ily of Logic. M onolithic Mem ories’ E C L 10KH devices are com pletely equivalent to M otorola’s M E C L 10KH. This

Contextual Info: ECL10KH High-Speed Emitter-Coupled Logic Family MC10H101 Quad OR/NOR Gate Features/ Benefits Ordering Inform ation • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H101 • Noise margin 150 mV PACKAGE TEMPERATURE { J,N,NL 20

fairchild 11c90

Abstract: SP888 SP8680B
Contextual Info: PLESSEY SEMICONDUCTORS 1 2E D 7220513 00GT775 S Sem iconductors SP8680B 600MHz - 10/11 TheSP8680 is an ECL counter with both ECL10K and i n ­ compatible outputs. The circuit can operate from either ECL or TTL supplies. The division ratio is controlled by two

SP8690

Abstract: DS3647-1 SP8690B plessey SP8691 SP8691/A/DG ECL10K SP8691 GEC Plessey 32
Contextual Info: ADVANCE INFORMATION DS3647-1•2 410/11 SP8690 200MHz4 48/9 SP8691 200MHz4 The SP8690 and SP8691 are low power ECL variable modulus dividers, with both ECL10K and TTL/CMOS compatible outputs. They divide by the lower division ratio when either of the ECL control inputs, PE1 or PE2, is in the high state and by

SP8695ADG

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3648-1•2 SP8695 200MHz4 410/11 The SP8695 is a low power ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3658-1•2 42 SP8602 500MHz4 42 SP8604 300MHz4 The SP8602 and SP8604 are emitter coupled logic dividers which feature ECL10K compatible outputs when used with

Contextual Info: Prelim inary HM10500 Series 262,144 Words x 1-Bit Fully Decoded Random Access Memory • DESCRIPTION HM10500-15 is ECL10K compatible, 262,144-words x 1-bit, read/ write random access memory developed for high speed systems such as main memories for super computers.

Contextual Info: ECL100K COMPATIBLE 4-BIT PROGRAMMABLE LOGIC DELAY LINE # E C L 1 0 0 K in p u t and o u tp u t levels # Delays stable and precise # 24-pin D IP package .3 7 5 high # A vailable in delays up to 77.8ns # A vailable in 18 delay steps w ith resolution The fro m 0.1 to 5.0ns

ecl100

Contextual Info: very lewprofile ECL100K COMPATIBLE LOGIC DELAY MODULE 100K ECL input and outputs The 10 0 K ECL LDM is offered in nineteen 1 9 delays from 9ns Delays stable and precise to 80 n s , w ith each module incorporating taps at 1 2 .5 % 24-pin DIP package (.3 0 0 high)

Contextual Info: ECL DIGITAL DELAY LINES E10 SERIES - ECL10K INTERFACED E100 SERIES - ECL100K INTERFACED Industry’s widest selection! 5nS - 200nS 500nS avail. Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

MC10H101

Abstract: ECL10KH
Contextual Info: ECL10KH High-Speed Em itter-Coupled Logic Fam ily M C10H101 Quad O R/NO R Gate Ordering Inform ation Features/B enefits • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H101 PACKAGE TEMPERATURE J,N,NL 20 Com • Noise margin 150 mV

Contextual Info: GEC; P L E S S E Y S I M I O N L IJ Cl I U A D V A N C E IN F O R M A T IO N It S DS3643-1-2 SP8647 250MHz h- 10/11 The SP8647 is an ECL variable modulus divider, with ECL10K and TTL/CMOS compatible outputs. It divides by 10 when eitherof the ECL control inputs, PE1 or PE2, s in the high

Contextual Info: GEC PLESSEY [ s e m i c o n d u c t o r s PRELIMINARY INFORMATION 1 SP2001 100MHz DIRECT DIGITAL FREQUENCY SYNTHESISER Supersedes January 1991 Edition The SP2001 Direct Frequency Synthesiser (DFS) is an ECL100K compatible ‘numerically controlled oscillator' i.e. it

10H507

Abstract: mecl10h
Contextual Info: M M O T O R O LA Military 10H507 Triple 2 Input Exclusive “OR’VExclusive “NOR” Gate ELECTRICALLY TESTED PER: 5962-8772701 H The 10H507 is a triple 2 input Exclusive OR/NOR gate. This M ECL10H part is a functional/pinout duplication of the standard MECL 10K family part, with

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ADVANCE INFORMATION DS3646-1•2 SP8685 500MHz4 410/11 The SP8685 is an ECL variable modulus divider, with ECL10K compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high state and by 11