DM54LS125A Search Results

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AW DM74LS125AM DM74LS125AN E20A J14A
Contextual Info: NATIONAL SENICOND -CLOGIO 31E D bSGliaa QGbTöbB 3 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description that two outputs will attempt to take a common bus to oppo­ site logic levels, the disable time Is shorter than the enable time of the outputs.

54LS125

Abstract: 54LS125A 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125A DM54LS125AJ DM54LS125AW DM74LS125A DM74LS125AM
Contextual Info: 54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125AM DM74LS125AN E20A
Contextual Info: June 1989 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description This device contains lour independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

54LS125ADMQB

Abstract: 54LS125AFMQB 54LS125ALMQB DM54LS125AW DM74LS125AM DM74LS125AN E20A J14A 54LS125
Contextual Info: LS125A a National Semiconductor 54LS125A/DM54LS125A/OM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

ls125a

Contextual Info: LS125A National Semiconductor 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description that two outputs will attempt to take a common bus to oppo­ site logic levels, the disable time is shorter than the enable time of the outputs. This device contains four independent gates each of which

Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers General Description cant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the

U1221

Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers This device contains fo u r independent gates each of which perform s a non-inverting buffer function. The outputs have the 3-STATE feature. W hen enabled, the outputs exhibit the low im pedance characteristics o f a standard LS output with

H9720

Abstract: m06g Marking Code SMD databook 937DMQB jm38510/10201bca 5962-8866207NA national semiconductor databook Motorola transistor smd marking codes DM54LS279J lm723
Contextual Info: N MILITARY / AEROSPACE DESIGN/PROCESS CHANGE NOTIFICATION PCN Nr: 1997 Listing GIDEP Nr: GIDEP Category: Issued: 01/21/97 TRB Nr: This is to advise you that a Design and/or Process Change will be made to the following MIL/AERO product s : Product ID (Description):

DM74LS125A

Abstract: DM54LS125AW DM74LS125AM DM74LS125AN 54LS125 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ
Contextual Info: DM74LS125A Quad 3-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with

JX - 638

Abstract: 54LS125A
Contextual Info: June 1989 5 4 L S 12 5A /D M 5 4L S 12 5A /D M 74 L S 1 25 A Quad TR I-STA TE B uffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125A DM74LS125AM DM74LS125AN E20A
Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers cant load nor as a driver. To m inim ize th e possibility th a t two outputs will attem pt to ta ke a com m on bus to opposite logic levels, th e disable tim e is shorter than the enable tim e of the