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    CY7C1302 Price and Stock

    Infineon Technologies AG CY7C1302DV25-167BZC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    Rochester Electronics LLC CY7C1302DV25-167BZC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    DigiKey CY7C1302DV25-167BZC Tray 10
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    Infineon Technologies AG CY7C1302DV25-167BZXC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    Avnet Americas CY7C1302DV25-167BZXC Tray 0 Weeks, 2 Days 33
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    Rochester Electronics LLC CY7C1302DV25-167BZXC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    DigiKey CY7C1302DV25-167BZXC Tray 10
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    Flip Electronics CY7C1302DV25-167BZXC

    IC SRAM 9MBIT PAR 167MHZ 165FBGA
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    DigiKey CY7C1302DV25-167BZXC Tray 25
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    CY7C1302 Datasheets (18)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C130-25DC Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF
    CY7C130-25LC Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF
    CY7C130-25LC Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF
    CY7C130-25PC Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF
    CY7C1302CV25 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302CV25-100 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302CV25-133 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302CV25-133BZC Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302CV25-167 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302CV25-167BZC Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25-100 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25-100BZXC Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25-133 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25-167 Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25-167BZC Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302DV25-167BZXC Cypress Semiconductor 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Original PDF
    CY7C1302V25 Cypress Semiconductor 9-Mb Pipelined SRAM with QDRTM Architecture Original PDF

    CY7C1302 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1302CV25

    Abstract: 1e77
    Text: CY7C1302CV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time


    Original     		PDF CY7C1302CV25 167-MHz CY7C1302CV25 1e77

    QDR cypress burst of two

    Abstract: Cypress QDR CY7C1302V25 CY7C1304V25
    Text: QDR SRAMs Fact Sheet Product Overview Cypress's family of Quad Data Rate™ QDR™ SRAMs offers customers the bandwidth improvement that high-speed applications demand. The family currently consists of 2 devices: The CY7C1302V25, with its burst length of 2, and the


    Original     		PDF CY7C1302V25, CY7C1304V25, 512Kx18 2-200QDRF QDR cypress burst of two Cypress QDR CY7C1302V25 CY7C1304V25

    CY7C1302V25

    Abstract: CY7C1302V25-133BZC
    Text: yy 7c1302V25: Rev 1.0 Revised: February 15, 2000 CY7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth


    Original     		PDF 7c1302V25: CY7C1302V25 167-MHz CY7C1302V25 CY7C1302V25-133BZC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302V25 167-MHz CY7C1302V25

    CY7C1302DV25

    Abstract: CY7C1302DV25-167 3M Touch Systems
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		PDF CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 3M Touch Systems

    CY7C1302DV25

    Abstract: CY7C1302DV25-167 5N25
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 5N25

    CY7C1302DV25

    Abstract: No abstract text available
    Text: CY7C1302DV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time


    Original     		PDF CY7C1302DV25 167-MHz CY7C1302DV25

    Untitled

    Abstract: No abstract text available
    Text: yy CY7C1302BV25 Preliminary 9 Mb Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302BV25 CY7C1302BV25 38-05XXX

    2L60

    Abstract: SAMSUNG os application note 3N62 CY7C1302V25
    Text: CY7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent read and write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5-ns clock-to-valid access time • Two-word burst on all accesses


    Original     		PDF CY7C1302V25 167-MHz CY7C1302V25 2L60 SAMSUNG os application note 3N62

    CY7C1302DV25

    Abstract: CY7C1302DV25-167
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167

    CY7C1302V25

    Abstract: 6n38 11x15
    Text: CY7C1302V25 ADVANCE INFORMATION 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302V25 167-MHz CY7C1302V25 6n38 11x15

    Untitled

    Abstract: No abstract text available
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Functional Description Features • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		PDF CY7C1302DV25 167-MHz

    CY7C1302V25

    Abstract: No abstract text available
    Text: yy CY7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302V25 167-MHz CY7C1302V25

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		PDF CY7C1302DV25 CY7C1302DV25 3M Touch Systems

    CY7C1304

    Abstract: spartan 2 CY7C1302 virtex 5 ddr data path
    Text: Interfacing the QDR to the XILINX SPARTAN-II FPGA CY7C1302 Figure 1 shows the block diagram of the CY7C1302 QDR device. Address /WPS Data In QDR is a family of synchronous SRAMs with an innovative architecture. This was designed particularly for high performance networking systems by the QDR Consortium, which


    Original     		PDF CY7C1302 CY7C1302 CY7C1304 CY7C1304 spartan 2 virtex 5 ddr data path

    CY7C1302CV25

    Abstract: No abstract text available
    Text: CY7C1302CV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time


    Original     		PDF CY7C1302CV25 167-MHz CY7C1302CV25

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		PDF CY7C1302DV25 CY7C1302DV25 3M Touch Systems

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■


    Original     		PDF CY7C1302DV25 CY7C1302DV25 3M Touch Systems

    CY7C1302V25

    Abstract: CY7C1302V25-167
    Text: CY7C1302V25 ADVANCE INFORMATION 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302V25 167-MHz CY7C1302V25 CY7C1302V25-167

    CY7C1302DV25

    Abstract: CY7C1302DV25-167
    Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time


    Original     		PDF CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167

    CY7C1302

    Abstract: 2X18 CY7C1304
    Text: Interfacing the QDR to the Delta39K™ QDR™: An Introduction With the continuos demand for higher performance data processing systems, memory devices are evolving to more closely match the needs of these applications. Specialized memory products that optimize memory bandwidth for a specific system architecture are successfully increasing overall


    Original     		PDF Delta39KTM Delta39KTM Delta39K CY7C1302 2X18 CY7C1304

    vhdl code for multiplication on spartan 6

    Abstract: CY7C1302 XAPP183 XAPP173
    Text: White Paper: Spartan-II R WP111 v1.0 February 16, 2000 Introduction Spartan-II Family as a Memory Controller for QDR-SRAMs Authors: Amit Dhir, Krishna Rangasayee The explosive growth of the Internet is boosting the demand for high-speed data communication systems. While RISC CPU speeds have exceeded clock rates of 500 MHz,


    Original     		PDF WP111 com/xapp/xapp173 xapp174 xapp179 wp106 XAPP183: vhdl code for multiplication on spartan 6 CY7C1302 XAPP183 XAPP173

    fast sram 100mhz

    Abstract: CLK180 SRAM timing CY7C1302V25 XAPP262 XC2V250 qdr sram di35 vhdl code for DCM
    Text: Application Note: Virtex-II Family R Quad DataRate QDR SRAM Interface for Virtex-II Devices XAPP262 (v1.0) January 15, 2001 Summary The Virtex -II family of FPGAs provides access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip distributed RAM and block RAM features, Virtex-II FPGAs


    Original     		PDF XAPP262 CY17C1302V25 fast sram 100mhz CLK180 SRAM timing CY7C1302V25 XAPP262 XC2V250 qdr sram di35 vhdl code for DCM

    ebe switches

    Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35
    Text: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • CY7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible


    OCR Scan     		PDF CY7C130/CY7C131 CY7C140/CY7C141 20O1V CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY7C131/CY7C140/ ebe switches CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35