CY7B992 Search Results

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 •■mmmmggf ¿mw Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

Contextual Info: CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR Programmable Skew Clock Buffer PSCB Features Functional Description • Output pair skew < 100 ps typical (250 max.) • All outputs skew <250 ps typical (500 max.) • 3.75- to 80-MHz output operation • User-selectable output functions

2t transistor

Abstract: dot matrix printer circuit diagram datasheet CY7B991 CY7B9911 CY7B992 MC10E101 MC10E163 R3000
Contextual Info: fax id: 3604 Innovative CY7B991/CY7B992 RoboClock Application Introduction This application note presents a unique application of RoboClock, using its complex and precise waveform generation capability to implement PWM (Pulse Width Modulation) to enhance color images and increase the resolution of laser

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

CY7B991

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation

CY7B991-7JI

Abstract: CY7B991 7B991 CY7B992 CY7B991-7LMB
Contextual Info: 92 CY7B991 CY7B992 Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can

CY7B9910

Abstract: CY7B9920 BUT12
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs

7B991

Abstract: CY7B991 CY7B992 MS2525
Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can

4 mhz oscillator

Abstract: phase shift oscillator Three phase oscillator 80960CA CY7B991 CY7B992
Contextual Info: fax id: 3610 Generation of Synchronized Processor Clocks Using the CY7B991 or CY7B992 Introduction 10 ns. In addition, the maximum cycle-to-cycle CLKIN period variation is plus or minus 0.1%. Another requirement is that the RESET input to the processor be held LOW for at least

CY7B991

Abstract: CY7B992
Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All Output Pair Skew <100 ps Typical 250 ps maximum ■ 3.75 MHz to 80 MHz Output Operation ■ User Selectable Output Functions ❐ Selectable Skew to 18 ns ❐ Inverted and Non-inverted

CY7B991

Abstract: program plc xf0 CY7B992 todc
Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All Output Pair Skew <100 ps Typical 250 ps maximum ■ 3.75 MHz to 80 MHz Output Operation ■ User Selectable Output Functions ❐ Selectable Skew to 18 ns ❐ Inverted and Non-inverted

CY7B185

Abstract: CY7B922 clock buffer FITS CY7B991 CY7B992 EME-6300H SM23B CY7B991-LMB
Contextual Info: Qualification Report February, 1994 QTP# 92202&93462 Version 2.0 PROGRAMMABLE SKEWCLOCK BUFFER CY7B991 TTL CY7B992 (CMOS) QUALIFICATION REPORT February, 1994 Version 2.0 QTP # 92202/93462 PROGRAMMABLE SKEW CLOCK BUFFER CY7B991 (TTL) CY7B992 (CMOS) CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

Contextual Info: CY7B991 CY7B992 CYPRESS Programmable Skew Clock Buffer PSCB Features All output pair skew <100 ps typical (250 max.) 3.75- to 80-M Hz output operation User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted — Operation at 1/ 2 and 1/ 4 input frequency

Contextual Info: CYPRESS SEMICONDUCTOR b5E T> 2 5 0 ^ 2 QQ1Q7T2 CYP CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR TÔ2 P rogram m ab le Skew C lock B u ffer P S C B Functional Description • Output pair skew <100 ps typical (250 max.) • All outputs skew <250 ps typical

tb99

Abstract: 005133a 0021336 CY78991 5 CY7B991 CY7B992 LOW11 RMS141
Contextual Info: fax id: 3515 CY7B991 CY7B992 CYPRESS Programmable Skew Clock Buffer PSCB Features • All output pair skew <100 ps typical (250 max.) • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted

2T transistor surface mount

Abstract: phase shift oscillator Cypress handbook Cypress Semiconductor application handbook MECL System Design Handbook transistor 2Fn dip guard capacitor motorola C 547 motorola mecl system design handbook pll pcb design
Contextual Info: fax id: 3603 Everything You Need to Know About CY7B991/2 RoboClock , CY7B9911 (RoboClock+), and CY7B9910/20 (Robo Jr.) Introduction TEST The following application note provides a detailed description of the CY7B991, CY7B9911, and CY7B992 Programmable Skew Clock Buffers (PSCB). It also provides an overview of

CY7B991-5JC

Abstract: CY7B991 7B991 CY7B992
Contextual Info: fax id: 3515 1CY 7B9 92 CY7B991 CY7B992 Programmable Skew Clock Buffer PSCB Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can