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Infineon Technologies AG CY2DP1502ZXIT IC CLK BUFFER 1:2 1.5GHZ 8TSSOP
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CY2DP1502ZXIT Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY2DP1502ZXIT		Cypress Semiconductor	Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8TSSOP		Original	PDF

CY2DP1502ZXIT Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz	Original	CY2DP1502 CY2DP1502 20-ps 480-ps 15-ps 12-kHz 20-MHz	PDF
Untitled Abstract: No abstract text available Text: CY2DP1502 1:2 LVPECL Fanout Buffer Functional Description Features • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz	Original	CY2DP1502 20-ps 480-ps 15-ps 12-kHz 20-MHz CY2DP1502	PDF
JESD78B Abstract: cy2d Text: CY2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One low-voltage positive emitter-coupled logic LVPECL input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■	Original	CY2DP1502 CY2DP1502 20-ps 480-ps 15-ps 12-kHz 20-MHz JESD78B cy2d	PDF
"differential input" common mode voltage LVDS Abstract: JESD78B Text: CY2DP1502 1:2 LVPECL Fanout Buffer 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input	Original	CY2DP1502 CY2DP1502 20-ps 480-ps 15-ps "differential input" common mode voltage LVDS JESD78B	PDF
JESD78B Abstract: No abstract text available Text: CY2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz	Original	CY2DP1502 20-ps 480-ps 15-ps 12-kHz 20-MHz CY2DP1502 JESD78B	PDF
JESD78B Abstract: No abstract text available Text: CY2DP1502 1:2 LVPECL Fanout Buffer 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input	Original	CY2DP1502 CY2DP1502 20-ps 480-ps 15-ps JESD78B	PDF