CY2308SC Search Results

EME-6300

Abstract: 84-1MISR4 CY2305SC CY2308
Contextual Info: Cypress Semiconductor Qualification Report QTP# 96303 VERSION 1.0 May 1997 Zero Delay Buffer CY2308SC 3.3V Zero Delay Buffer 16 Pins, 150 mil SOIC CY2309SC Low Cost 3.3V Zero Delay Buffer (16 Pins, 150 mil SOIC) CY2305SC Low Cost 3.3V Zero Delay Buffer (8 pins, 150 mil SOIC)

CY2308SC-1H

Abstract: CY2308 CY2308-1 CY2308-1H CY2308-2 CY2308-3 CY2308-4 23086 REF05
Contextual Info: fax id: 3526 1CY 230 8 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low skew outputs — Output-output skew less than 250 ps

transistor smd marking BA

Abstract: NTT08HC NTH23HB NTHA6HC PLA004 st416hf-50 NTH03HB SOJ-20 NTHA3HB ST413HC
Contextual Info: Pericom Semiconductor Corp. • 3545 North First St. • San Jose, CA 95134 • USA PRODUCT DISCONTINUANCE NOTIFICATION PDN PDN Number: 06-0201 Issue Date: February 17, 2006 Product(s) Affected: Please see the attached EOL product list Alternative Supply Sources: Also visit Pericom's website for other

CY2308-1

Abstract: CY2308 CY2308-1H CY2308-2 CY2308-3 CY2308-4 REF05
Contextual Info: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by ca­ pacitive load on FBK input • Multiple configurations, see “Available CY2308 Config­ urations” table • Multiple low skew outputs — Output-output skew less than 250 ps

CY2308E

Abstract: CY2308SXI
Contextual Info: CY2308 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for

CY23085

Contextual Info: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low skew outputs — Output-output skew less than 200 ps

TP24-TP28

Abstract: A19N CY1352 33pF50V CER-0805
Contextual Info: 5 4 3 2 1 Mezzanine Connections pages 4-5 CT_C8_A CT_C8_B CT_FRAME_A CT_FRAME_B CT_D[31:0] CT_NETREF1 CT_NETREF2 CT_MC MC_CLOCK MC_RX MC_TX CT_C16_NEGATIVE CT_C16_POSITIVE CT_FR_COMP CT_C2 CT_C4 CT_SCLK CT_SCLKX2 General (pages 2-3) MTPLL_PRI MTPLL_SEC MTPLL_LOS1

CPU-A13

Abstract: R32237 10uf,16v 10uf16v CTD12 CER-0805
Contextual Info: 5 4 3 2 1 Mezzanine Connections TXA_CLK TXA_SOC TXA_PAR TXA_ENBTXA_CLAV TXA_DATA[7:0] General MTPLL_FS1 MTPLL_FS2 MTPLL_TCLRMTPLL_RSTMTPLL_RSEL MTPLL_LOS1 MTPLL_LOS2 MTPLL_MS1 MTPLL_MS2 MTPLL_PRI MTPLL_SEC D RXA_CLK RXB_CLK RXC_CLK TXA_CLK TXB_CLK TXC_CLK

Contextual Info: CY2308 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for

CY2308SXC-1

Abstract: CY2308SXI-1H CY2308 CY2308SI-XX CY2308SXI
Contextual Info: 1CY2308 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

Contextual Info: 8 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

Contextual Info: 1CY2308 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

1H08S

Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
Contextual Info: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -

Contextual Info:  CY2308 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for

CY2308SC-1T

Abstract: CY2308SI-2T 164-05A06SL CY2308SC-2T CY2308SC-5HT CY2308SXC-2T CY2308 CY2308SXI CY2308SC-3T
Contextual Info: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations, see “Available CY2308 Configurations” on page 3 ■ Multiple low skew outputs ■ Two banks of four outputs, three-stateable by two select

K26 ZL

Abstract: ssram 80MHZ AD29 MT90502 MT90503 MT92210 MT92220 msan configuration
Contextual Info: MSAN-222 Minimizing the Number of External SSRAM Chips on Zarlink Packet Processors Application Note Contents Issue 2 bits wide, making 512Kx18 the largest size of SSRAM chip that can be used. Normally multiple SSRAM chips have to be used in order to achieve the maximum

REF05

Contextual Info: 1CY2308 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

CY2308

Abstract: CY2308-1 CY2308-1H CY2308SI-XX REF05
Contextual Info: 8 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

CY2308

Contextual Info: CY2308 3.3V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the Select inputs as shown in the table “Select Input Decoding” on page 2”. If all output clocks are not required, Bank B is three-stated. The input clock is directly

CY2304

Abstract: CY2308
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 98204 VERSION 2.0 October, 2000 Zero Delay Buffer, 3.3V L28 Technology, Fab 2 CY2305/CY2309 10-MHz to 100/133-MHZ CY2304/CY2308 10-MHz to 133-MHZ CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell

CY2308

Abstract: CY2308SI-4
Contextual Info: CY2308 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for

Contextual Info: V CYPRESS Features • Zero input-output propagation delay, adjustable by ca­ pacitive load on FBK input • Multiple configurations, see “Available CY2308 Config­ urations” table • Multiple low skew outputs — Output-output skew less than 200 ps

Contextual Info: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low-skew outputs • Two banks of four outputs, three-stateable by two select

Contextual Info: CY2308 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for