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    CSP2510C

    Abstract: No abstract text available
    Text: 3.3V PHASE-LOCK LOOP CLOCK DRIVER FEATURES: IDTCSP2510C PRODUCT PREVIEW FBOUT output to the clock (CLK) input signal. It is specifi­ ca lly designe d for use w ith synchronou s DRAMs. The CSP251OC operates at 3.3V and provides integrated seriesdamping resistors that make it ideal for driving point-to-point


    OCR Scan     		IDTCSP2510C 24-pin 133MHz: 100ps 133MHz 25MHz 140MHz CSP2510C PDF