AT40KAL Search Results

mq4 datasheet

Abstract: fifo buffer fifo vhdl AT40K AT40KAL AT94K MQ-3
Contextual Info: IP Core Generator: Fast FIFO Implementation Features • • • • • FIFO Depth Up to 128 Clock Speed Up to 56 MHz Implementation Uses FreeRAM in Architecture Customizable Full and Empty Signals Available from the IP Core Generator for AT40K, AT40KAL and AT94K FPSLIC™

atmel 306

Abstract: atmel 438 atmel 228 atmel 836 vhdl code for carry select adder atmel 1202 vhdl code for 64 carry select adder vhdl code for flip flop 64 verilog code for johnson counter carry select adder vhdl
Contextual Info: IP Core Generator Features • • • • • • • • Schematic Generation AT40K & AT40KAL Symbol Generation (AT40K & AT40KAL) Hard Macro Generation User-defined Macro Name User-defined Pins User-defined Libraries Flat Netlist Generation for Simulation

Contextual Info: Features • Functionally and Pin Compatible with the Atmel Rad Hard AT40KAL Series • Ultra High Performance • • • • • • • • • • • – System Speeds to 85 MHz – Array Multipliers > 45 MHz – 14 ns Flexible SRAM – Internal Tri-state Capability in Each Cell

4263B

Abstract: ATDH40D160M vhdl for 8 point fft AT17 AT40K AT40K20 AT40KAL AT40KAL040 ATDH40M ATDS2100PC
Contextual Info: Features • Functionally and Pin Compatible with the Atmel Rad Hard AT40KAL Series • Ultra High Performance • • • • • • • • • • • – System Speeds to 85 MHz – Array Multipliers > 45 MHz – 14 ns Flexible SRAM – Internal Tri-state Capability in Each Cell

7805T

Abstract: LM7805 D2 PACK IOD10 IOA10 IOA18 IOA14 5310 ci 74c14 317t IOA21
Contextual Info: Features • Hardware – Supports Programming for Atmel AT40K/AT40KAL and AT94KALSeries of SRAM-based Programmable System Level Integration PSLI Devices – Supports ISP (In-System Programming) for Atmel AT17 Series Configuration EEPROMs – Built-in Clock Source with GCLK/FCLK Jumper Settings

AT40K

Abstract: AT40K-PCI
Contextual Info: Features • pci_mt Function Implementing a 32-bit Component Interconnect PCI Interface Optimized for AT40K/AT40KAL/AT94K Architecture • Extensive Simulation Testing, Includes Test Vectors • Uses 585 Core Cells • Fully-compliant Design Including: – 32-bit, 33 MHz Operation

FCK111

Abstract: AT40K AT40K20 AT40K40AL AT40KAL AT40KAL040 AT40KEL O348 o372
Contextual Info: Features • Standard Military Version: AT40KAL • Radiation and SEU Hardened Version: AT40KEL • AT40KAL and AT40KEL are Functionally and Pin Compatible with the Atmel Commercial AT40K40AL Series • Ultra High Performance • • • • • • • •

atmel 432

Contextual Info: AT40K05AL, AT40K10AL AT40K20AL, AT40K40AL 5K – 50K Gates Coprocessor FPGA with FreeRAM SUMMARY DATASHEET Features  Ultra High Performance ̶ ̶ System Speeds to 100MHz Array Multipliers > 50MHz 10ns Flexible SRAM Internal Tri-state Capability in Each Cell

2431B

Abstract: AT40KAL AT94K AT94KAL AT40K
Contextual Info: IP Core Generator: Decoder Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices Variable Output Logic Level Variable Width of Input Vectors

Inverter Gates

Abstract: AT40K AT40KAL AT94K AT94KAL
Contextual Info: IP Core Generator: Logic Gates Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices Variable Width of Input and Output Data

Integrated Development System

Abstract: puretech AT40K AT40KAL ATDH40M ATDM2100PC ATDM2100SN ATDS2100PC ATDS2100SN verilog code for routing table
Contextual Info: Contents Atmel FPGA Integrated Development System IDS contains the following items: • IDS Installation Guide • CD-ROM containing all necessary software and online documents Features • • • • • • • • • • • • • • • • •

atmel 426

Abstract: AT40K AT40KAL AT94K
Contextual Info: IP Core Generator: Constant Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices • Variable Width of Output Vectors • Constant Value • Binary, Octal, Decimal or Hexadecimal Radix Value

LFSR COUNTER

Abstract: LFSR johnson counter ctr16 johnson counter LFSR AT40K AT40KAL AT94K AT94KAL simple LFSR
Contextual Info: IP Core Generator: Counter Features • • • • • • • • • • • • • Counter – Johnson Counter – LFSR Counter – PreScaled Counter – Ripple Carry Counter – Terminal Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for

Contextual Info: Features • Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store • • • • • • • • • • • • Configuration Programs for Field Programmable Gate Arrays FPGAs 3.3V Output Capability 5V Tolerant I/O Pins In-System Programmable (ISP) via 2-wire Bus

2445A

Abstract: AT40K AT40KAL AT94K atmel 24 ROM16
Contextual Info: IP Core Generator: ROM Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices Variable Width of Address Inputs Variable Width of ROM Data

pulse generator

Abstract: AT40K AT40KAL AT94K 2443A-12
Contextual Info: IP Core Generator: Pulse Generator Features • Pulse Generator – Fixed • Pulse Generator – Loadable • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices

AT40K

Abstract: AT40KAL AT94K AT94KAL
Contextual Info: IP Core Generator: Transparent Latch Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices Variable Width of Input and Output Data

subtractor

Abstract: 8 bit subtractor AT40K AT40KAL AT94K
Contextual Info: IP Core Generator: Subtractor Features • Subtractor – Carry Select • Subtractor – Ripple Carry • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices

AT40K

Abstract: AT40KAL AT94K
Contextual Info: IP Core Generator: Bus Ripper Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices • Variable Width of Input Bus • Used for Schematic Designs Only

ATMEL 218

Abstract: fif16 AT40K AT40KAL AT94K AT94KAL atmel 458
Contextual Info: IP Core Generator: FIFO Features • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices • Variable Width of Parallel Input and Output Data • Variable Depth of FIFO

ATDH40M

Abstract: FIGARO LM7805 M 5962-0325002QYC IN4001 diode INFORMATION AT17 AT17LV010 AT40KEL ATDH2225 ATMEl 837
Contextual Info: AT40KEL-DK Design Kit . User Guide Table of Contents Section 1 Introduction . 1-1

Contextual Info: Features • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party

AT17F32

Abstract: AT24CXXX AT40K AT40KAL AT94K AT94KAL ATDH2200E ATDH2225 ATDH2200
Contextual Info: Features • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party

ATDH2200

Abstract: AT17F32A AT17F32A-30BJI AT40K AT40KAL AT94KAL ATDH2200E ATDH2225
Contextual Info: Features • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party