ALVC10 Search Results

4634

Abstract: IDT74ALVC10
Contextual Info: ALVC10 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE ALVC10 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE DESCRIPTION: FEATURES: – – This triple 3-input positive-NAND gate is built using advanced dual metal CMOS technology. The ALVC10 performs the Boolean function

Contextual Info: ALVC10 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE INDUSTRIAL TEMPERATURE RANGE ALVC10 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE DESCRIPTION: FEATURES: This triple 3-input positive-NAND gate is built using advanced dual metal CMOS technology. The ALVC10 performs the Boolean function Y = A • B

A115-A

Abstract: C101 SN74ALVC10 SN74ALVC10D
Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106F – JULY 1997 – REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA

Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

A115-A

Abstract: C101 SN74ALVC10 SN74ALVC10D
Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

Contextual Info: 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 4 0 ° C to +85°C

Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

Contextual Info: 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1.27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 40°C to +85°C

Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

A115-A

Abstract: SN74ALVC10 SN74ALVC10D SN74ALVC10DR SN74ALVC10NSR
Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106E – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)

A115-A

Abstract: C101 SN74ALVC10 SN74ALVC10D
Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

"NAND Gate"

Abstract: 3 input nand gate data sheet 4634
Contextual Info: ALVC10 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ALVC10 ADVANCE INFORMATION 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE DESCRIPTION: FEATURES: This triple 3-input positive-NAND gate is built using advanced dual

Contextual Info: R ALVC10 ADVANCE INFORMATION 3.3V CMOS TRIPLE 3-INPUT POSITIVE-NANDGATE _ irr I i D E S C R IP T IO N : FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP and

A115-A

Abstract: C101 SN74ALVC10 SN74ALVC10D
Contextual Info: ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE www.ti.com SCES106H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per