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    8701 CLOCK Search Results

    8701 CLOCK Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    8701CYILFT Renesas Electronics Corporation Low Skew, ÷1,÷2 Clock Generator Visit Renesas Electronics Corporation
    8701CYILF Renesas Electronics Corporation Low Skew, ÷1,÷2 Clock Generator Visit Renesas Electronics Corporation
    87016AYILF Renesas Electronics Corporation Low Skew,1-to-16 LVCMOS/LVTTL Clock Generator Visit Renesas Electronics Corporation
    87016AYILFT Renesas Electronics Corporation Low Skew,1-to-16 LVCMOS/LVTTL Clock Generator Visit Renesas Electronics Corporation
    8701CYLF Renesas Electronics Corporation Low Skew, ÷1,÷2 LVCMOS/LVTTL Clock Generator Visit Renesas Electronics Corporation

    8701 CLOCK Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    8701 clock

    Abstract: No abstract text available
    Text: DBS 8700/8701 High Precision Digitizers 16-Bit at 200 kHz or 400 kHz in a “C” Size VXI Module Introduction The DBS 8700/8701 features the first 200 kHz/400 kHz, high resolution, multichannel Digitizing Systems that combine the superior precision of 16-bit


    Original     		PDF 16-Bit Hz/400 16-bit 16-Bit, 8701 clock

    ic cmos 4095

    Abstract: 5652 XC25BS3 XC25BS5 XC25BS8 "frequency multiplier" KHz MHz
    Text: 8F Sakura Nihonbashi Bldg., 1-13-12, Nihonbashikayaba-cho, Chuo-ku, Tokyo 103-0025 Japan Tel: +81-3-5652-8700 Fax: +81-3-5652-8701 http://www.torex.co.jp/english/ PRESS RELEASE TRX036 June 2, 2008 XC25BS8 Series PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits


    Original     		PDF TRX036 XC25BS8 XC25BS3 XC25BS5. OT-26W2 ic cmos 4095 5652 XC25BS5 "frequency multiplier" KHz MHz

    100MHz FREQUENCY DIVIDER

    Abstract: Frequency multiplier 1mHz 100MHz transistor 6c x 5652 XC25BS7 1MHz Frequency Generator ic
    Text: 8F Sakura Nihonbashi Bldg., 1-13-12, Nihonbashikayaba-cho, Chuo-ku, Tokyo 103-0025 Japan Tel: +81-3-5652-8700 Fax: +81-3-5652-8701 http://www.torex.co.jp/english/ PRESS RELEASE ＴＲＸ028 September 14, 2007 XC25BS7 Series PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits


    Original     		PDF XC25BS7 100MHz FREQUENCY DIVIDER Frequency multiplier 1mHz 100MHz transistor 6c x 5652 1MHz Frequency Generator ic

    MCAB 035060-33

    Abstract: axial bead 105 at 100MHz 035060-33 bead axial BEAD INDUCTORS MCAB 035090-33
    Text: MCAB Series Axial Ferrite Bead Inductors Features: • Applications include suppression in digital equipment and clock circuits. • Supplied bandoliered on reels of 5000 suitable for automatic insertion. Shape Specifications Minimum Impedance Ω Ω Bead Dimensions


    Original     		PDF 10MHz 100MHz MCAB 035060-33 axial bead 105 at 100MHz 035060-33 bead axial BEAD INDUCTORS MCAB 035090-33

    Untitled

    Abstract: No abstract text available
    Text: ICS8701 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8701 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs


    Original     		PDF ICS8701 ICS8701 200ps 250ps 300ps 600ps

    Untitled

    Abstract: No abstract text available
    Text: ICS8701 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8701 is a low skew, ¸1, ¸2 Clock Generator and a member of the HiPerClockS™ HiPerClockS family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs


    Original     		PDF 200ps 250ps 300ps 600ps ICS8701 ICS8701

    Untitled

    Abstract: No abstract text available
    Text: REVISIONS PART NO. MCAB 035075-33 Ferrite Bead Inductors ECN # REV DESCRIPTION DRAWN DATE CHECKD DATE APPRVD DATE - A RELEASED S. R 8/5/06 K. S 8/5/06 N. K 22/5/06 Features: • • • Axial ferrite bead inductors. Applications include suppression in digital equipment and clock circuits.


    Original     		PDF AB0350 M10000215

    NS32201

    Abstract: LK 2816 LK 1623 NS32016 0C16 4C16 C1995 NS32202 NS32203-10 M4116
    Text: June 1988 NS32203-10 Direct Memory Access Controller General Description Features The NS32203 Direct Memory Access Controller DMAC is a support chip for the Series 32000 microprocessor family designed to relieve the CPU of data transfers between memory and I O devices The device is capable of packing


    Original     		PDF NS32203-10 NS32203 16-bit NS32201 LK 2816 LK 1623 NS32016 0C16 4C16 C1995 NS32202 M4116

    Untitled

    Abstract: No abstract text available
    Text: REVISIONS PART NO. TO BNC 40-58 ECN # REV DESCRIPTION DRAWN DATE CHECKD DATE APPRVD DATE - A RELEASED S. K 16/6/06 K. S 16/6/06 N. K 30/6/06 Electrical Specifications: Impedance Frequency Minimum Insulation Resistance Maximum Inner Contact Resistance Maximum Outer Contact Resistance


    Original     		PDF 5000M. 500VRMS. 1500VRMS. -55dB M10000364

    Analogic Corporation

    Abstract: No abstract text available
    Text: DBS 8710 16-Bit Precision, 16-Channel Multiplexer – Simultaneous S/H in a “C” Size VXI Module Introduction The DBS 8710 is the first high speed, high precision multiplexer that combines 16 very accurate sample-and-hold S/H channels with a 400 kHz aggregate


    Original     		PDF 16-Bit 16-Channel 16-channel, Log10 AD-1046 8710-B05 8700-B05 8701-B05 Analogic Corporation

    GB 2510

    Abstract: DDR 333 AS4DDR16M72PBG AS4DDR32M72PBG 80314
    Text: 1.2 Gb / 2.4 Gb SDRAM-DDR MCP OPTIMUM DENSITY, FLEXIBILITY AND PERFORMANCE PRODUCT FAMILY MEMBERS: AS4DDR16M72PBG 1.2 Gb, SDRAM-DDR, 16M x 72/80, 32 mm x 25 mm - 219 PGBA 2.4 Gb, SDRAM-DDR, 32M x 72/80, 32 mm x 25 mm - 219 PGBA AS4DDR32M72PBG KEY PRODUCT FEATURES


    Original     		PDF AS4DDR16M72PBG AS4DDR32M72PBG DQ49-64 DQ65-80 16/32M 266Mbps GB 2510 DDR 333 AS4DDR16M72PBG AS4DDR32M72PBG 80314

    transistor ckx

    Abstract: TUNDRA AS4DDR232M72PBG AS4DDR264M72PBG ground bus 25mm
    Text: 2.4 Gb / 4.8 Gb SDRAM-DDR MCP OPTIMUM DENSITY, FLEXIBILITY AND PERFORMANCE PRODUCT FAMILY MEMBERS: AS4DDR232M72PBG KEY PRODUCT FEATURES AS4DDR264M72PBG ™ DDR2 Data rate = 667, 533, 400 ™ Available in Industrial, Enhanced and Extended Temp ™ Package: ¾ 255 Plastic Ball Grid Array PBGA ,


    Original     		PDF AS4DDR232M72PBG AS4DDR264M72PBG MPC7447A MPC7448 Tsi110) MPC8641 MPC8641D transistor ckx TUNDRA AS4DDR232M72PBG AS4DDR264M72PBG ground bus 25mm

    linear 50 Ohm Line Drivers

    Abstract: ICS8701
    Text: HiPerClockSTM Application Note Integrated Circuit Systems, Inc. Power Dissipation For High Speed LVCMOS Buffer This application note describes the power dissipation and junction temperature calculation for LVCMOS clock buffers with series termination and parallel termination. ICS8701 is used as an


    Original     		PDF ICS8701 linear 50 Ohm Line Drivers

    hyperlynx

    Abstract: lvcmos
    Text: HiPerClockSTM Application Note Integrated Circuit Systems, Inc. High Speed LVCMOS Driver Termination Design Guide This application note provides general design guide for high speed LVCMOS driver termination. To handle high speed LVCMOS drivers, general rules for high-speed digital board design must be carefully followed. Improper


    Original     		PDF

    led clock circuit diagram

    Abstract: ECL IC NAND ic 3842 datasheet DAC ic 0808 pin diagram 3842 smps IC 8 pin ic 3842 MCK12140 application note ADC 10 Ghz 266 XnOR GATE NB3N551
    Text: Complete Clock Management Solutions Processor Skew Tuning 1 HCSL TTL-to-PECL Translator Multiplexer LVDS TTL/CMOS LVDS/HCSL Loop Filter VCO 10 ZDB ASIC Memory 1 CMOS/TTL Divider/ Prescaler PE/EQ Processor 9 1 Discrete PLL Blocks Processor 5 1 PECL/CML Phase


    Original     		PDF BRD8042-4 BRD8042/D led clock circuit diagram ECL IC NAND ic 3842 datasheet DAC ic 0808 pin diagram 3842 smps IC 8 pin ic 3842 MCK12140 application note ADC 10 Ghz 266 XnOR GATE NB3N551

    W8701

    Abstract: instruction set Sun SPARC T3 Cy7C601 weitek 8701 W8701-40 weitek instruction set Sun SPARC T5 w8720 a2054
    Text: W8701 INTEGRATED SPARC-COMPATIBLE PROCESSOR FAMILY M arch 1992 Chapter 1. Technical Overview 1.1. Features SINGLE-CHIP SPARC-COMPATIBLE IU/FPU HIGH PERFORMANCE Combines SPARC-compatible integer and floating-point units on a single chip Highest-performance SPARC-compatible processor on


    OCR Scan     		PDF W8701 207-pin 8701-025-GCD630 instruction set Sun SPARC T3 Cy7C601 weitek 8701 W8701-40 weitek instruction set Sun SPARC T5 w8720 a2054

    TSC8701CL

    Abstract: TSC8700CJ tsc8701 TSC8700 LX5700 7906 regulator TSC8700CL TSC8702 8702r LX5700A
    Text: TELEDYNE COMPONENTS SäE D â'ilTt.üa DÜGS573 1 "PTTELEDYNE SEMICONDUCTOR The Analog Signal Processing Company TSC8700 TSC8701 TSC8702 " BINARY OUTPUT ADCs r -s i-io -o i FEATURES • High Accuracy — Up to 12-Bli Resolution With <±1 /2 LSB Error ■ Tight DNL of <±1/2 LSB


    OCR Scan     		PDF GS573 TSC8700 TSC8701 TSC8702 12-Bli TSC8700 TSC8701CL TSC8700CJ LX5700 7906 regulator TSC8700CL TSC8702 8702r LX5700A

    NS32201

    Abstract: No abstract text available
    Text: NS32203-10 PRELIMINARY £51 National ä ü Semiconductor NS32203-10 Direct Memory Access Controller General Description Features The NS32203 Direct Memory Access Controller DMAC Is a support chip for the Series 32000* microprocessor family designed to relieve the CPU of data transfers between


    OCR Scan     		PDF NS32203-10 NS32203-10 NS32203 16-bit NS32201 TL/EE/8701 TL/EE/8701-31 TL/EE/8701-33

    54ALS162

    Abstract: GDFP2-F16 GDIP1-T16
    Text: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED Convert to military drawing format. Change V|L, fMAx, tp, CLOCK, l|L, and propagation delays. Remove vendor CAGE 04713._ 86-09-02 N. A. Hauck Change fanout, synchronous clear pulse width, enable P/enable T setup time, and


    OCR Scan     		PDF 5962-R133-92. 5962-R335-92 SNJ54ALS162AFK M38510/381 02B2X 0EU86 54ALS162 GDFP2-F16 GDIP1-T16

    NS32201

    Abstract: rial mow S3220 NS32016 NS32203-10 32203 cpu RSN 312 H 24 NS32202 AOS PACKING M4116
    Text: NS32203-10 PRELIMINARY National 4lA Semiconductor NS32203-10 Direct Memory Access Controller General Description Features The NS32203 Direct Memory Access Controller DMAC is a support chip for the Series 32000 microprocessor family designed to relieve the CPU of data transfers between


    OCR Scan     		PDF NS32203-10 NS32203 16-bit NS32201 TL/EE/8701-34 NS32203-10 NS32016 AI6-23 KS32201 NS32203 rial mow S3220 32203 cpu RSN 312 H 24 NS32202 AOS PACKING M4116

    TSP60C18

    Abstract: TSP60C20
    Text: TSP60C18 SPEECH DATA ROM 3.0 TSP60C18 GENERAL DESCRIPTION THE TSP60C18 IS A 256K BIT ROM FABRICATED IN CMOS TECHNOLOGY FOR LOW OPERATING AND STANDBY POWER CONSUMPTION. THE DESIGN IS OPTIMIZED FOR THE DATA STORAGE REQUIREMENTS FOR SYSTEMS WITH LIMITED I/O CAPABILITY.


    OCR Scan     		PDF TSP60C18 28-PIN TSP60C20

    TSP60C81

    Abstract: No abstract text available
    Text: TSP60C81 SPEECH DATA ROM 6.0 TSP60C81 GENERAL DESCRIPTION THE TSP60C81 IS A 1 MEGA BIT ROM FABRICATED IN CMOS TECHNOLOGY FOR LOW OPERATING AND STANDBY POWER CONSUMPTION. THE DESIGN IS OPTIMIZED FOR THE DATA STORAGE REQUIREMENTS FOR SYSTEMS WITH LIMITED I/O CAPABILITY.


    OCR Scan     		PDF TSP60C81 28-PIN

    TSP50C50

    Abstract: TSP50C4X TSP60C19 paralell input serial output shift register
    Text: TSP60C19 SPEECH DATA ROM 4.0 TSP60C19 GENERAL DESCRIPTION THE TSP60C19 IS A 256K BIT ROM FABRICATED IN CMOS TECHNOLOGY FOR LOW OPERATING AND STANDBY POWER CONSUMPTION. THE DESIGN IS OPTIMIZED FOR THE DATA STORAGE REQUIREMENTS OF SYNTHETIC SPEECH SYSTEMS BUT MAY


    OCR Scan     		PDF TSP60C19 28-PIN TSP50C50 TSP50C4X paralell input serial output shift register

    TSP50C4X

    Abstract: TSP60C20
    Text: TSP60C80 SPEECH DATA ROM 5.0 TSP60C80 GENERAL DESCRIPTION THE TSP60C80 IS A 1 M BIT ROM FABRICATED IN CMOS TECHNOLOGY FOR LOW OPERATING AND STANDBY POWER CONSUMPTION. THE DESIGN IS OPTIMIZED FOR THE DATA STORAGE REQUIREMENTS OF SYNTHETIC SPEECH SYSTEMS BUT MAY


    OCR Scan     		PDF TSP60C80 28-PIN TSP50C4X TSP60C20