82C0 Search Results

difference between intel 8086 and intel 80186 pro

Abstract: 82C08 intel 82c08 difference between intel 80186 and intel 80286 pro 82C08-8 80188 programming 82C08-10 intel 80186 pin out IC 8208 intel 8208
Contextual Info: in te i. 82C08 CHMOS DYNAMIC RAM CONTROLLER • ■ 0 Walt State with INTEL ^Processors iAPX 286 1 10, 8 MHz J iAPX 186/88 1 86/88 J 82C08-20 20 MHz 82C08-16 16 MHz 82C08-10 10 MHz 82C08-8 8 MHz ■ Supports 64K and 256K DRAMs (256K x 1 and 256K x 4 Organizations)

82c08

Abstract: smd transistor A7 5962R9571401QRC 5962R9571401QXC 5962R9571401VRC 5962R9571401VXC HS1-82C08RH-8 HS-82C08RH HS9-82C08RH-8 30403 smd
Contextual Info: HS-82C08RH TM Data Sheet August 2000 File Number Radiation Hardened 8-Bit Bus Transceiver Features The Intersil HS-82C08RH is a radiation-hardened octal bus transceiver with three-state outputs. It is manufactured using a self-aligned, junction isolated CMOS process and is

82c08

Abstract: 5962R9571401QRC 5962R9571401QXC 5962R9571401VRC 5962R9571401VXC HS-82C08RH CERAMIC FLATPACK
Contextual Info: HS-82C08RH Radiation Hardened 8-Bit Bus Transceiver February 1996 Features Functional Diagram • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95714 and Intersil’ QM Plan

Contextual Info: HS-82C08RH HARRIS S E M I C O N D U C T O R Radiation Hardened 8-Bit Bus Transceiver August 1995 Features Functional Diagram • Radiation Hardened - Total Dose 1 x 105 RAD Si - Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s AO ' • Bidirectional Three-State Input/Outputs

2164 dynamic ram

Abstract: intel 8203 2164A 8202a intel microprocessor pin diagram 8202A intel 4002 8088 ram 256K pin diagram of intel IC 8203 diagram of IC 8203 Intel 2164
Contextual Info: in t e i 82C03 CMOS 64K DYNAMIC RAM CONTROLLER • Provides All Signals Necessary to NMOS 2164A and CMOS Control (51C64) 64K Dynamic Memories Internal Clock Capability ■ Directly Addresses and Drives Up to 64 Devices Without External Drivers Provides System Acknowledge and Trans­

sem 3040

Abstract: sem 3040 ic
Contextual Info: f|ì HARRIS HS-82C08RH S E M I C O N D U C T O R Radiation Hardened 8-Bit Bus Transceiver December 1992 Pinouts Features 20 PIN CERAMIC DIP CASE OUTUNE D8, CONFIGURATION 3 • Radiation Hardened - Total Dose 1 x 10s RAD Si TOP VIEW - Latch-Up Im m une EPI-CM OS > 1 x 1012 RAD(Siys

5962R9571401QRC

Abstract: 5962R9571401QXC 5962R9571401VRC 5962R9571401VXC HS-82C08RH
Contextual Info: HS-82C08RH S E M I C O N D U C T O R Radiation Hardened 8-Bit Bus Transceiver February 1996 Features Functional Diagram • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95714 and Harris’ QM Plan

Contextual Info: in te i 82C03 CMOS 64K DYNAMIC RAM CONTROLLER Provides All Signals Necessary to NMOS 2164A and CMOS Control (51C64) 64K Dynamic Memories • Provides Refresh/Access Arbitration ■ Internal Clock Capability ■ Directly Addresses and Drives Up to 64 Devices Without External Drivers

Contextual Info: Î H U H v A R R HS-82C08RH I S S E M I C O N D U C T O R Radiation Hardened 8-Bit Bus Transceiver D e c e m b e r 1992 Features Pinouts • Radiation Hardened 20 PIN CERAMIC DIP CASE OUTLINE D8, CONFIGURATION 3 - Total Dose 1 x 105 RAD Si - Latch-Up Immune EPI-CMOS > 1 x 1012 RAD(Siys

.B07 smd

Contextual Info: HS-82C08RH 3 Radiation Hardened 8-Bit Bus Transceiver February 1996 Functionai Diagram Features • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95714 and Harris’ QM Plan

intel i5 block diagram

Abstract: DYNAMIC RAM CONTROLLER intel 82c08 82C08 INTEL 32 lead PLCC 8208 intel IC 8208 82C06 82C08-10 b237
Contextual Info: intei 82C08 CHMOS DYNAMIC RAM CONTROLLER 0 Wait State with INTEL ^Processors iAPX 286 82C08-20 20 MHz 10, 8 MHz) I 82C08-16 16 MHz iAPX 186/88 } 82C08-10 10 MMz 86/88 I 82C08-8 8 MHz Supports 64K and 256K DRAMs (256K x 1 and 256K x 4 Organizations) Power Down Mode with Programmable

Contextual Info: in te i- 82C08 CHMOS DYNAMIC RAM CONTROLLER • 0 Wait State with INTEL ^Processors ■ ÌAPX 286 I 10, 8 MHz J iAPX 186/88 1 86/88 J 82C08-20 20 MHz 82C08-16 16 MHz 82C08-10 10 MHz 82C08-8 8 MHz ■ Directly Addresses and Drives up to 1 Megabyte without External Drivers

ic 8057 block diagram

Contextual Info: HS-82C08RH 33 Radiation Hardened 8-Bit B u s T ran sceiver February 1996 Features Functional Diagram • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95714 and Harris’ QM Plan

RE 4TP

Abstract: 273tp 82C03
Contextual Info: in te i 82C03 CMOS 64K DYNAMIC RAM CONTROLLER • Provides All Signals Necessary to NMOS 2164A and CMOS Control (51C64) 64K Dynamic Memories ■ Internal Clock Capability ■ Directly Addresses and Drives Up to 64 Devices Without External Drivers ■ Provides System Acknowledge and Trans­

8A13

Abstract: BCA02 82c094 BA21 Omega 82c194 Trident Microsystems
Contextual Info: Omega 82C194 / Trident Product B rief ’ CardBus/PCMCIA Host Adapter Controller Features High Performance Small Form Factor • Supports up to 33 MHz CardBus with peak bandwidth of 132 MB/sec • Single chip PCMCIA host controller • Built-in PCI-WAY, SIBP, and ISA Legacy IRQ directly

RJP 30 h1

Contextual Info: TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Highest-Performance Floating-Point Digital D D D D D D Signal Processor DSP : TMS320C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word

Contextual Info: TMS320C6712D FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Low-Price/High-Performance Floating-Point D D D D D Digital Signal Processor DSP : TMS320C6712D − Eight 32-Bit Instructions/Cycle − 150-MHz Clock Rate

Contextual Info: www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 1.1 • • • • • • Features High-Performance Digital Media Processor

Contextual Info: TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218H − MAY 2003 − REVISED JUNE 2006 D Highest-Performance Fixed-Point Digital D D D D D Signal Processors DSPs − 1.67-, 1.39-ns Instruction Cycle Time − 600-, 720-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

Contextual Info: SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 D Controlled Baseline D D D D D D D D L1/L2 Memory Architecture − One Assembly/Test Site, One Fabrication

C6000

Abstract: TMS320C6000 TMS320C6411
Contextual Info: TMS320C6411 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS196I − MARCH 2002 − REVISED JUNE 2005 D Low-Cost, High-Performance Fixed-Point D D D D DSP − TMS320C6411 − 3.33-ns Instruction Cycle Time − 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

Contextual Info: TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS SPRS226F − NOVEMBER 2003 − REVISED MARCH 2005 D Highest-Performance Fixed-Point DSPs D D D D D − 1.67-/1.39-/1.17-/1-ns Instruction Cycle − 600-/720-/850-MHz, 1-GHz Clock Rate

TMS320DM642

Abstract: A-600 C6000 DM642 IEC60958-1 TMS320C6000 sprs200n TMS 3834 AED0
Contextual Info: TMS320DM642 www.ti.com SPRS200N – JULY 2002 – REVISED OCTOBER 2010 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Check for Samples: TMS320DM642 1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 123 • High-Performance Digital Media Processor

Contextual Info: SM320DM642-EP www.ti.com SGUS058D – JUNE 2007 – REVISED OCTOBER 2010 SM320DM642-EP Video/Imaging Fixed Point Digital Signal Processor Check for Samples: SM320DM642-EP 1 SM320DM642-EP Video/Imaging Fixed-Point Digital Signal Processor 123 • Controlled Baseline