74LVX27 Search Results

LVX273

Abstract: 74LVX273 74LVX273M 74LVX273MTC 74LVX273MTCX 74LVX273MX 74LVX273SJ 74LVX273SJX M20D
Contextual Info: LVX273 National Semiconductor & 74LVX273 Low Voltage Octal D Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset

74LVX27

Contextual Info: 74LVX27 LOW VOLTAGE TRIPLE 3-INPUT NOR GATE . HIGH SPEED: tpD =4.1 ns TYP. at Vcc = 3.3V . INPUT VOLTAGE LEVEL: V il = 0.8V, V ih = 2V at Vcc = 3V . LOW POWER DISSIPATION: Icc = 2 |oA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at Vcc = 3.3V

74LVX273

Abstract: 74LVX273M 74LVX273MTR 74LVX273TTR
Contextual Info: 74LVX273 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

74LVX273MTC

Abstract: 74LVX273SJ LVX273 M20D MTC20 74LVX273 74LVX273M
Contextual Info: 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

74LVX273

Abstract: 74LVX273M 74LVX273MTC 74LVX273MTCX 74LVX273MX 74LVX273SJ 74LVX273SJX LVX273 M20D
Contextual Info: 74LVX273 Low Voltage Octal D Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously

74LVX273

Abstract: 74LVX273M 74LVX273MTR 74LVX273TTR
Contextual Info: 74LVX273 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

74LVX27

Abstract: 74LVX27M 74LVX27MTR 74LVX27TTR TSSOP14
Contextual Info: 74LVX27 LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

LVX273

Abstract: 74LVX273 74LVX273M 74LVX273MTC 74LVX273SJ M20D MTC20 DIODE SJ 98
Contextual Info: E M IC D N D U C T O R t 74LVX273 Low Voltage Octal D Flip-Flop G eneral D escription The LVX273 has eight edge-triggered D -type flip-flops with individual D inputs and Q o u tp uts. The com m on buffered C lock CP and M aster Reset (MR) input load and reset

74LVX27

Abstract: 74LVX27MTR 74LVX27TTR TSSOP14
Contextual Info: 74LVX27 LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX273

Abstract: 74LVX273M 74LVX273MTC 74LVX273SJ LVX273 M20D MS-013 MTC20
Contextual Info: Revised March 1999 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

Contextual Info: S E M IC O N D U C T O R 74LVX273 Low Voltage Octal D Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-tlops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

74LVX27

Abstract: 74LVX27M 74LVX27MTR 74LVX27TTR TSSOP14
Contextual Info: 74LVX27 LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX273

Abstract: 74LVX273MTR 74LVX273TTR 74LVX27
Contextual Info: 74LVX273 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

74LVX27

Abstract: 74LVX27M TSSOP14
Contextual Info: 74LVX27  LOW VOLTAGE TRIPLE 3-INPUT NOR GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.1 ns TYP. at VCC = 3.3V INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V

74LVX27

Contextual Info: 74LVX27 LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

LVX273

Abstract: 74LVX273 74LVX273M 74LVX273T P013L
Contextual Info: 74LVX273  LOW VOLTAGE OCTAL D-TYPE FLIP FLOP WITH CLEAR WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz TYP. at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V

LVX273

Abstract: KFIR
Contextual Info: LVX273 S 3 National ÆÆ Semiconductor 74LVX273 Low Voltage Octal D Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-tlops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset

LVX273

Abstract: 74LVX273 74LVX273M 74LVX273T
Contextual Info: 74LVX273  LOW VOLTAGE OCTAL D-TYPE FLIP FLOP WITH CLEAR WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz TYP. at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V

74LVX27

Abstract: 74LVX27M 74LVX27MTR 74LVX27TTR TSSOP14
Contextual Info: 74LVX27 LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX273

Contextual Info: 74LVX273 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

Contextual Info: A I R C H June 1993 I L D Revised March 1999 S E M [CONDUCTOR TM 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset

74LVX273

Abstract: 74LVX273M 74LVX273MTC 74LVX273SJ LVX273 M20D MS-013 MTC20
Contextual Info: Revised April 2005 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset

74LVX273

Abstract: 74LVX273M 74LVX273MTC 74LVX273SJ LVX273 M20D MS-013 MTC20
Contextual Info: Revised September 2003 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset

B5011A

Abstract: Box58090 MSC 5511 74LVX273
Contextual Info: tSüllEB 007flflSl ^a? • NSC1 gg National ÆÆ Semiconductor January 1994 74LVX273 Low Voltage Octal D Flip-Flop General Description Features The ’ LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered