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    74LVC1 Search Results

    74LVC1 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LVC1G123DCURE4 Texas Instruments Single Retriggerable Monostable Multivibrator with Schmitt-Trigger Inputs 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    74LVC1G125DBVRG4 Texas Instruments Single Bus Buffer Gate With 3-State Outputs 5-SOT-23 -40 to 125 Visit Texas Instruments Buy
    74LVC1G139DCUTG4 Texas Instruments 2-Line-to-4-Line Decoder 8-VSSOP -40 to 85 Visit Texas Instruments Buy
    74LVC1G175DBVRG4 Texas Instruments Single D-Type Flip-Flop with Asynchronous Clear 6-SOT-23 -40 to 125 Visit Texas Instruments Buy
    74LVC1G240DCKRE4 Texas Instruments Single Inverting Buffer/Driver With 3-State Outputs 5-SC70 -40 to 125 Visit Texas Instruments Buy
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    74LVC1 Price and Stock

    Texas Instruments SN74LVC125ARGYR

    IC BUF NON-INVERT 3.6V 14VQFN
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    DigiKey SN74LVC125ARGYR Digi-Reel 12,149 1
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    Texas Instruments SN74LVC126APWR

    IC BUF NON-INVERT 3.6V 14TSSOP
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    DigiKey SN74LVC126APWR Cut Tape 12,059 1
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    ComSIT USA SN74LVC126APWR 9,814
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    Component Electronics, Inc SN74LVC126APWR 247
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    Texas Instruments SN74LVC138AQPWRQ1

    IC DECODER/DEMUX 1X3:8 16TSSOP
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    Texas Instruments SN74LVC11ABQAR

    THREE-CHANNEL THREE-INPUT 1.2V-T
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    Texas Instruments SN74LVC14ANSR

    IC INVERT SCHMITT 6CH 1-INP 14SO
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    DigiKey SN74LVC14ANSR Cut Tape 2,543 1
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    Rochester Electronics SN74LVC14ANSR 384,177 1
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    Find more 74LVC1 price and stock on Findchips.com

    74LVC1 Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LVC10 Philips Semiconductors Triple 3-input NAND gate Original PDF
    74LVC109 Philips Semiconductors Dual JK flip-flop with set and reset, positive-edge trigger Original PDF
    74LVC109A Integrated Device Technology 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET, POSITIVE-EDGE TRIGGER, 5V TOLERANT I-O Original PDF
    74LVC109A Philips Semiconductors Dual J-k Positive Edge Triggered Flip-flop With Clear and Preset Original PDF
    74LVC109D Philips Semiconductors Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger Original PDF
    74LVC109D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LVC109D Philips Semiconductors Dual JK flip-flop with set and reset, positive-edge trigger Scan PDF
    74LVC109D Philips Semiconductors Dual JK flip-flop with set and reset, positive-edge trigger Scan PDF
    74LVC109D,112 NXP Semiconductors Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT109-1 (SO16); Container: Tube Original PDF
    74LVC109D,112 NXP Semiconductors 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch Original PDF
    74LVC109D,118 NXP Semiconductors Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13" Original PDF
    74LVC109D,118 NXP Semiconductors 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch Original PDF
    74LVC109DB Philips Semiconductors Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger Original PDF
    74LVC109DB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LVC109DB Philips Semiconductors Dual JK flip-flop with set and reset, positive-edge trigger Scan PDF
    74LVC109DB Philips Semiconductors Dual JK flip-flop with set and reset, positive-edge trigger Scan PDF
    74LVC109DB,112 NXP Semiconductors Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Tube Original PDF
    74LVC109DB,112 NXP Semiconductors 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch Original PDF
    74LVC109DB,118 NXP Semiconductors Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" Original PDF
    74LVC109DB,118 NXP Semiconductors 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch Original PDF
    ...

    74LVC1 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G14 Single Schmitt-trigger inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free


    Original     		74LVC1G14 74LVC1G14 PDF

    application note tssop5 nxp

    Abstract: No abstract text available
    Text: 74LVC1G06 Inverter with open-drain output Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		74LVC1G06 74LVC1G06 application note tssop5 nxp PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		74LVC1G08 74LVC1G08 771-LVC1G08GWDG125 74LVC1G08GW/DG PDF

    marking VU SOT363

    Abstract: No abstract text available
    Text: 74LVC1G11 Single 3-input AND gate Rev. 7 — 4 July 2012 Product data sheet 1. General description The 74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.


    Original     		74LVC1G11 74LVC1G11 marking VU SOT363 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.


    Original     		74LVC1GU04 74LVC1GU04 JESD22-A114F JESD22-A115-A PDF

    74LVC1G53

    Abstract: 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8
    Text: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 — 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select


    Original     		74LVC1G53 74LVC1G53 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8 PDF

    74LVC1G3157GV

    Abstract: 74LVC1G3157GW 74LVC1G3157 74LVC1G3157GF 74LVC1G3157GM JESD22-A114E
    Text: 74LVC1G3157 2-channel analog multiplexer/demultiplexer Rev. 02 — 18 September 2007 Product data sheet 1. General description The 74LVC1G3157 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select


    Original     		74LVC1G3157 74LVC1G3157 74LVC1G3157GV 74LVC1G3157GW 74LVC1G3157GF 74LVC1G3157GM JESD22-A114E PDF

    74LVC1G04

    Abstract: 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW JESD22-A114E MO-203
    Text: 74LVC1G04 Single inverter Rev. 08 — 27 April 2009 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		74LVC1G04 74LVC1G04 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW JESD22-A114E MO-203 PDF

    74LVC1G06

    Abstract: 74LVC1G06GF 74LVC1G06GM 74LVC1G06GV 74LVC1G06GW JESD22-A114E
    Text: 74LVC1G06 Inverter with open-drain output Rev. 07 — 12 July 2007 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		74LVC1G06 74LVC1G06 74LVC1G06GF 74LVC1G06GM 74LVC1G06GV 74LVC1G06GW JESD22-A114E PDF

    74LVC162244A

    Abstract: 74LVC162244ADGG 74LVC162244ADL 74LVCH162244A 74LVCH162244ADGG 74LVCH162244ADL SSOP48
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC162244A; 74LVCH162244A 16-bit buffer/line driver, 30 Ω series termination resistors; 5 V tolerant input/output; 3-state Product specification Supersedes data of 1998 Feb 17 2003 Dec 12 Philips Semiconductors Product specification


    Original     		74LVC162244A; 74LVCH162244A 16-bit 74LVC 62244A SCA75 R20/04/pp16 74LVC162244A 74LVC162244ADGG 74LVC162244ADL 74LVCH162244A 74LVCH162244ADGG 74LVCH162244ADL SSOP48 PDF

    74LVC16241A

    Abstract: 74LVC16241ADGG 74LVC16241ADL SSOP48 TSSOP48
    Text: 74LVC16241A 16-bit buffer/line driver with 5 V tolerant inputs/outputs; 3-state Rev. 03 — 16 February 2004 Product data sheet 1. General description The 74LVC16241A is a high-performance, low-power and low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.


    Original     		74LVC16241A 16-bit 74LVC16241A 74LVC16241ADGG 74LVC16241ADL SSOP48 TSSOP48 PDF

    74LVC16373A

    Abstract: 74LVC16373ADGG 74LVC16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL TSSOP48
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 2002 Oct 02 2003 Dec 08 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V


    Original     		74LVC16373A; 74LVCH16373A 16-bit 74LVC 6373A SCA75 74LVC16373A 74LVC16373ADGG 74LVC16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL TSSOP48 PDF

    74LVC1G58

    Abstract: 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW JESD22-A114E marking code 5
    Text: 74LVC1G58 Low-power configurable multiple function gate Rev. 04 — 27 April 2009 Product data sheet 1. General description The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


    Original     		74LVC1G58 74LVC1G58 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW JESD22-A114E marking code 5 PDF

    74LV157

    Abstract: 74LVC157A 74LVC157APW 74LVC157ADC
    Text: INTEGRATED CIRCUITS 74LVC157A Quad 2-input multiplexer Product specification Supercedes data of 1997 Nov 07 IC24 Data Handbook Philips Semiconductors 1998 Jul 29 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A input S . The four outputs present the selected data in the true


    Original     		74LVC157A 74LV157. 74LV157 74LVC157A 74LVC157APW 74LVC157ADC PDF

    74LVC1G74DC

    Abstract: 74LVC1G74 74LVC1G74DP 74LVC1G74GD 74LVC1G74GM 74LVC1G74GT
    Text: 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 9 — 5 August 2010 Product data sheet 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q


    Original     		74LVC1G74 74LVC1G74 74LVC1G74DC 74LVC1G74DP 74LVC1G74GD 74LVC1G74GM 74LVC1G74GT PDF

    74LVC1G332

    Abstract: 74LVC1G332GF 74LVC1G332GM 74LVC1G332GV 74LVC1G332GW
    Text: 74LVC1G332 Single 3-input OR gate Rev. 3 — 26 October 2010 Product data sheet 1. General description The 74LVC1G332 provides one 3-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		74LVC1G332 74LVC1G332 74LVC1G332GF 74LVC1G332GM 74LVC1G332GV 74LVC1G332GW PDF

    74LVC1G126

    Abstract: 74LVC1G126GF 74LVC1G126GM 74LVC1G126GV 74LVC1G126GW
    Text: 74LVC1G126 Bus buffer/line driver; 3-state Rev. 9 — 25 August 2010 Product data sheet 1. General description The 74LVC1G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A LOW-level at pin OE


    Original     		74LVC1G126 74LVC1G126 74LVC1G126GF 74LVC1G126GM 74LVC1G126GV 74LVC1G126GW PDF

    74LVC1G125GW

    Abstract: 74LVC1G125 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV VM MARKING CODE SOT353
    Text: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 8 — 24 August 2010 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE


    Original     		74LVC1G125 74LVC1G125 74LVC1G125GW 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV VM MARKING CODE SOT353 PDF

    74LVC1G57

    Abstract: 74LVC1G57GF 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW
    Text: 74LVC1G57 Low-power configurable multiple function gate Rev. 4 — 15 October 2010 Product data sheet 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


    Original     		74LVC1G57 74LVC1G57 74LVC1G57GF 74LVC1G57GM 74LVC1G57GV 74LVC1G57GW PDF

    74LVC1G157

    Abstract: 74LVC1G157GF 74LVC1G157GM 74LVC1G157GV 74LVC1G157GW
    Text: 74LVC1G157 Single 2-input multiplexer Rev. 4 — 28 October 2010 Product data sheet 1. General description The 74LVC1G157 is a single 2-input multiplexer which select data from two data inputs I0 and I1 under control of a common data select input (S). The state of the common data


    Original     		74LVC1G157 74LVC1G157 74LVC1G157GF 74LVC1G157GM 74LVC1G157GV 74LVC1G157GW PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC16373A-Q100; 74LVCH16373A-Q100 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 2 — 10 July 2014 Product data sheet 1. General description The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold 74LVCH16373A-Q100 only for


    Original     		74LVC16373A-Q100; 74LVCH16373A-Q100 16-bit 74LVC16373A-Q100 74LVCH16373A-Q100 LVCH16373A PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC16373A-Q100; 74LVCH16373A-Q100 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 1 — 24 June 2014 Product data sheet 1. General description The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches featuring separate D-type inputs with bus hold 74LVCH16373A-Q100 only for


    Original     		74LVC16373A-Q100; 74LVCH16373A-Q100 16-bit 74LVC16373A-Q100 74LVCH16373A-Q100 LVCH16373A PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G19 1-of-2 decoder/demultiplexer Rev. 7 — 10 September 2014 Product data sheet 1. General description The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y true and 2Y


    Original     		74LVC1G19 74LVC1G19 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Rev. 10 — 21 June 2011 Product data sheet 1. General description The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with 3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit


    Original     		74LVC16244A; 74LVCH16244A 16-bit 74LVCH16244A LVCH16244A PDF