74LS2 Search Results

74283 IC pin diagram

Abstract: IC 74283 74283 IC 8 bit pin diagram
Contextual Info: SN54283, SN54LS283, SN54S283, SN74283, SN 74LS283, SN74S283 4 BIT BINARY FU LL AD DERS W ITH FA S T CARRY OCTOBEH 1976 - REVISED MARCH 1988 S N 5 4 2 8 3 , S N 5 4 L S 2 8 3 . . . J OR W PAC KA G E S N 5 4 S 2 8 3 . . . J P AC K A G E S N 7 4 2 8 3 . . . N P AC K A G E

74LS266M

Abstract: LS266 74L826 74LS266
Contextual Info: TYPES SN54LS286, 74LS266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-COUECTOR OUTPUTS TTL MSI B U L L E T IN NO. D L-S 7611843, D E C E M B E R 1 9 7 2 - R E V IS E O O C T O B E R 1B7S S N 6 4LS 266 . . . J O R W P A C K A G E SN 74LS266. . . J OR N P A C K A S E

Contextual Info: SN54LS242, SN54LS243, 74LS242, 74LS243 QUADRUPLE BUS TRANSCEIVERS APHIL 1985 —REVISED MARCH 198B • T w o -W a y Asynchronous C om m unication B etw een D ata Buses • P N P Inputs Reduce D -C Loading SN 54LS 242, SN 54LS 243 . . . J OR W PACKAGE SN 74LS 242. SN 74LS243 . . . D OR N PACKAGE

IC 7428

Abstract: 74LS28 TTL 7428
Contextual Info: SN 5428, S N 54LS28, SN 7428, SN 74LS28 QUADRUPLE 2-INPUT POSITIVE NOR BUFFERS DECEM BER • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs SN 5428, SN54LS28 S N 7428. SN 74LS28 .

Contextual Info: 74LS295B Signetics Shift Register 4-Bit Shift Register With 3-State Outputs Product Specification Logic Products FEATURES • 4-bit parallel load shift register • Independent 3-State buffer outputs • See '395 for serial expansion and Master Reset version

TTL 74ls20

Contextual Info: SANYO SEMICONDUCTOR CORP b3E D • 7 cH 7 D 7 b 0011174 7 cìb W T S A J Ordering number: EN3910 MLC74HC20 No.3910 CMOS High-Speed Standard Logic Dual 4-Input NAND Gate F e a tu re s • The MLC74HC20 consists of 2 identical 4-input NAND gates. • Uses CMOS silicon gate process technology to achieve operating speeds sim ilar to LS • TTL 74LS20

LS244

Abstract: applications of 74LS244 74LS244 LOGIC DESCRIPTION 74LS244 LS241 74LS244 20 pin of 74LS244 74ls244 as buffer
Contextual Info: Am25LS241 • Arr»54LS/74LS241 Am25LS244• Am54LS/74LS244 O c ta l T h re e -S ta te B uffers DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • • • • • • • • The 'LS241 and 'LS244 are octal buffers fabricated using advanced low-pow er Schottky technology. The 20-pin pack­

C243

Abstract: 54LS242DM 54LS242FM 54LS243DM 74LS242DC 74LS242FC 74LS242PC 74LS243DC 74LS243FC 74LS243PC
Contextual Info: 242 • 243 C O N N E C T IO N D IA G R A M S P IN O U T A 54LS/74LS242 54LS/74LS243 ouo,n^ QUAD BUS TRANSCEIVER W ith 3-State O utputs 1,(7 n c g n d ] 7 | Vcc [T h ] e2 œ T7|nc E HI Œ in E I] I] (T D E S C R IP T IO N — T he 'LS 242 a n d ’243 are quad bus tra n s m itte rs /re c e iv e rs

M74LS240P

Abstract: la 7610 d 667c
Contextual Info: M ITSUBISHI L S T T L s M 74LS240P OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUTS INVERTED DESCRIPTION The M 74LS240P PIN CONFIGURATION (TOP VIEW) is a s e m ic o n d u c to r integrated c irc u it a n d c o m m o n o u tp u t c o n tro l in p u t f o r all 4 d iscrete c irc u its .

DN74LS22

Contextual Info: 74LS22 LS T TL DN74LS Series 74LS22 Dual 4 - input P o sitiv e NAND G ates with Open C ollector Outputs P-1 • Description DN 74LS22 contains tw o 4-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • • • •

74LS298PC

Abstract: 54298DM 54298FM 54LS298DM 74298DC 74298FC 74298PC 74LS298DC 74LS298FC LS298
Contextual Info: 298 C O N N E C T IO N D IA G R A M Ci I 54/74298 • 54LS/74LS298 <? !ù PINOUT A 'S . O' V I lib [T QUAD 2-PORT REGISTER Ila M u ltip le x e r w ith Storage Tiri vcc [7 T|] Qa loa[ï Qb lOb [_£ 73] Qc he [ T 1 2 ] Qd iid(T ÏT] c p To| s lod [ T GND [7

74LS258FC

Abstract: 74S258PC 74LS258 74LS258PC 54LS258DM 54S258DM 54S258FM 74LS258DC 74S258DC 74S258FC
Contextual Info: 258 C O N N E C T IO N D IA G R A M P IN O U T A '"54S /74S 258 0 / ^ / 7 54LS /74LS258 t>/6 /cjC, ; QUAD 2- I NPUT MULTIPLEXER s q With 3-State Outputs io«, { T T s lo l Ila f 3 H J lO c [ i i l Vcc Z a [T U K lob l~5~ H]Zc iib [F « ]lM z b[7 D E S C R IP T IO N — T h e ’258 is a quad 2 -in p u t m u ltip le x e r w ith 3 -sta te o u tp u ts.

DN74LS26

Contextual Info: I 74LS26 LS TTL DN74LS Series 74LS26 Quad 2 -input High-Voltage Interface P ositive NAND Gates P-1 U Description D N 74LS26 contains four 2-input positive isolation NAND b u ffer gate circuits. • Features • • • • • “ Wired” AND capability

74LS244PC

Abstract: 74LS240PC 74LS244 CLS240 C244 74S240PC C240 54C244 74LS241 74S241
Contextual Info: 240 • 241 • 244 acL-ii y C O N N E C T IO N D IA G R A M S P IN O U T A '" / f H g r 4S/74S240 • 54LS /74LS 240 54S/74S241 • '54LS/74LS241 0 / c ^ c<V 54LS /74LS 244ÎX r> O C T A L B U F F ^ F fÀ J lÌ È Ì D R I V E R With 3-State Outputs P IN O U T B

LS251

Abstract: 74LS151 multiplexers 74 LS 150 LS 74LS151 pin diagram 41 multiplexer 74ls151 74 LS 151 Logic DIAGRAM eight input multiplexer 54LS251 74LS1 74LS251
Contextual Info: Am25LS151 • Am54LS/74LS151 Am25LS251 • Am54LS/74LS251 Eight-Input Multiplexers L O G IC D IA G R A M D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • S w itches o n e -o f-e ig h t in p u ts to tw o co m p le m e n ta ry o u tp u ts S ta n d ard , 'L S 15 1 and three-state, 'L S 25 1 o u tp u t versions

bi 72

Abstract: BI 344
Contextual Info: PANASONIC INDL/ELEK -CIO 72 69 328 52 PANASONIC dËJ 1^33*52 □DQ717M 5 1 72C 0 7 1 7 4 I N D L * ELECTRONIC LS TTL DN74LSS>U—X D 74LS249/74LS249S - |- fr—* I I *-*J DN 74LS249/ DN 74LS249S B C D -to -7 -segment D ecorders/ D r iv e r s (with Open C ollector Outputs

DN74LS245

Abstract: MA161
Contextual Info: 74LS245 LS TTL DN74LS Series 74LS245 ro 74LS^4-S' O ctal Bus T r a n sc e iv e r s w ith 3 -sta te O u tp u ts • Description P-3 D N 74LS245 contains eight bus transm itter/receiver circuits with non-inverted outputs. ■ Features • • • • •

DN74LS253

Contextual Info: 74LS253 LS TTL DN74LS Series 74LS253 Dual 4 - line to 1 -lin e Data S e le c to r s/M u ltip le x e r s with 3 -s ta te Outputs • Description P-2 D N 74LS253 contains tw o 4-line to 1-line data selector/m ulti­ plexer circuits w ith 3-state outputs.

74LS299 APPLICATIONS

Abstract: 74LS299PC 74LS299DC 54LS299DM 54LS299FM 74LS299FC 74LS serial in shift register
Contextual Info: 299 54LS/74LS299 c I b -74 1 CONNECTION DIAGRAM PINOUT A 8-IN PU T UNIVERSAL SHIFT/STORAG E REGISTER W ith C om m on Parallel I/O Pins DESCRIPTION — The ’299 is an 8-bit universal shift/storage register w ith 3state outputs. Four modes of operation are possible: hold (store), shift left,

4 inputs OR gate truth table

Abstract: 74LS20 TTL 74ls20 truth table NAND gate 74 74Ls20 truth table 751A-02 4 inputs OR gate datasheet truth table NOT gate 74 74LS20 2 input SN74LSXXN
Contextual Info: SN54/74LS20 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

74LS245 application

Abstract: logic diagram of 74LS245 74ls245 74ls245 motorola TTL 5400 motorola SN54/74LS245 751d-03 SN54LSXXXJ SN74LSXXXN motorola TTL 5400
Contextual Info: SN54/74LS245 OCTAL BUS TRANSCEIVER The SN54 / 74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input (E) can be used

74ls290

Abstract: LS290 74LS293 751A-02 LS293 LS90 LS93 74LS293 Asynchronous counter
Contextual Info: SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The SN54 / 74LS290 and SN54/ 74LS293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five LS290 or divide-by-eight (LS293) section

74LS299 APPLICATION NOTE

Abstract: 74LS299 74LS299 APPLICATIONS SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS299 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Four modes of operation are possible: hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the

74LS259

Abstract: demultiplexer truth table SN54/74LS259 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS259 8-BIT ADDRESSABLE LATCH The SN54/ 74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and