lm294oct
Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
Text: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12
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74LS00
74LS01
74LS02
74LS03
74LS04
74LS05
74LS06
74LS07
74LS08
74LS09
lm294oct
d71054c
D71055C
lm294oct-12
74c928
7486 XOR GATE
interfacing ADC 0808 with 8086 microprocessor
555 7490 7447 7 segment LED display
Motorola 74LS76
NEC D71055C
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SC74HC595
Abstract: SC74HC595C SC74HC595D sc74hc
Text: SC74HC595 8 3S SC74HC595 8 CMOS / 8 SOP-16-300-1.27 54LS/74LS SOP-16-225-1.27 54LS/74LS SSOP-16-300-0.65 SCK RCK SCK SI RCK SCLR DIP-16-300-2.54 TSSOP-16-225-0.65 G * 2~6V * 1µA * 15 * * SC74HC595 DIP-16-300-2.54 SC74HC595A SOP-16-225-1.27 fmax=55MHz VCC=5V
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SC74HC595
OP-16-300-1
54LS/74LS
OP-16-225-1
SSOP-16-300-0
DIP-16-300-2
TSSOP-16-225-0
SC74HC595
SC74HC595C
SC74HC595D
sc74hc
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LS623
Abstract: D2537 SN74LS620
Text: S N 54LS 620, SN 54LS621, SN 74LS 620, SN 74LS 621, SM 74LS623 OCTAL BUS TRANSCEIVERS D2537, AUGUST 1979-REVISEO MARCH 1988 SN 54LS620, S N 54LS621, S N & 4 L S 6 2 2 . . . J P AC K A G E S N 74LS 620, S N 74LS621, S N 7 4 L S 6 2 3 . . . D W O R N P AC K A G E
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54LS621,
74LS623
D2537,
1979-REVISEO
20-Pin
54LS620,
74LS621,
LS623
D2537
SN74LS620
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Untitled
Abstract: No abstract text available
Text: AVG DDi Semiconductors Technical Data 192, 193 Synchronous Up/Down Decade and Binary Counters with CLEAR DV74LS192 DV74ALS192 DV74LS193 DV74ALS193 The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary
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DV74LS192
DV74ALS192
DV74LS193
DV74ALS193
74LS/ALS192
74LS/ALS193
MODULO-16
ALS192
LS192
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Untitled
Abstract: No abstract text available
Text: AVG DDi Semiconductors Technical Data DV74LS190 DV74ALS190 DV74LS191 DV74ALS191 Synchronous Up/Down Decade and Binary Counters The 74LS/ALS 190 is a synchronous UP/DOWN BCD Decade counter 8421 The 74LS/ALS 191 is a synchronous UP/DOWN Modulo-16 Binary Counter. State changes of the counters are
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DV74LS190
DV74ALS190
DV74LS191
DV74ALS191
74LS/ALS
Modulo-16
ALS190
LS190
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IC 74LS14
Abstract: 74ls14 74LSxx ic 74ls13
Text: M OTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The S N 54LS /74LS 13 and SN 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into
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/74LS
SN54/74LS13
SN54/74LS14
IC 74LS14
74ls14
74LSxx
ic 74ls13
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54LS244
Abstract: No abstract text available
Text: LS244 National Semiconductor 54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description • Typical Iq i_ sink current 54LS 12 mA 74LS 24 mA ■ Typical Ioh (source current) 54LS - 1 2 mA 74LS - 1 5 mA ■ Typical propagation delay times
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54LS244/DM74LS244
667il
667ii
667fi
667fl
667ii
54LS244
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74LS24
Abstract: DM54LS244J DM74LS244WM 54LS 74LS DM74LS244N J20A DM54LS244
Text: DM54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description • Typical Io l sink current 54LS 12 mA 74LS 24 mA ■ Typical Ioh (source current) 54LS - 1 2 mA 74LS - 1 5 mA ■ Typical propagation delay times Inverting 10.5 ns
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DM54LS244/DM74LS244
133ii.
74LS24
DM54LS244J
DM74LS244WM
54LS
74LS
DM74LS244N
J20A
DM54LS244
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74ALS192
Abstract: IC 74LS192 LS192 ALS192 MODULO-16 DV74LS192 DV74LS192-93 LS193
Text: AVG Semiconductors DDT Technical Data The 74LS/ALS192 is an UP/DOWN BCD Decade 8421 Counter and the 74LS/ALS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The out
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74LS192
74ALS192
74LS/ALS193
MODULO-16
clock92-93,
DV74ALS192-93
1-800-AVG-SEMI
LS192,
ALS192,
LS192
IC 74LS192
ALS192
DV74LS192
DV74LS192-93
LS193
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Untitled
Abstract: No abstract text available
Text: 25LS194A 4-Bit Universal Shift Register 25LS195A 4-Bit Parallel-Access Shift Register FEATURES • ■ PIN-OUT DIAGRAM Higher speed compared to 9LS/54LS and 9LS/74LS 8mA sink current over full military temperature range ■ 50m V improved V o l compared to 9LS/74LS
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25LS194A
25LS195A
9LS/54LS
9LS/74LS
440/xA
12-BIT
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4QFC
Abstract: S62D
Text: SN54LS595, SN54LS596, SN74LS595, SN74LS596 8 BIT SH IFT REGISTERS W ITH O U TPU T LATC H ES 02634, JANUARY 1981 - REVISED MARCH 1988 S N 54LS 595, SN64LS596 . . . J OR W PACKAGE SN 74LS 595, S N 74LS 596 . . . N PACKAGE 8-Bit Serial-ln, Parallel-Out Shift
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SN54LS595,
SN54LS596,
SN74LS595,
SN74LS596
XS596)
SN64LS596
LS595
LS596
4QFC
S62D
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction
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54/74LS
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20-PIN
Abstract: M74LS37P
Text: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES
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M74LS37P
M74LS37P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
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74LS299 APPLICATIONS
Abstract: No abstract text available
Text: M MOTOROLA SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The S N 54/74LS 323 is an 8-Bit Universal S hift/S torage Register with 3-state outputs. Its function is sim ilarto the SN 54/74LS 299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are
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SN54/74LS323
54/74LS
SN54/74LS323
74LS299 APPLICATIONS
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74LS18P
Abstract: No abstract text available
Text: MITSUBISHI LSTTLs M 74LS 18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS 18P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing tw o 4-input positive-logic N A N D gates having a schm itt trigger function and negative-logic N O R gates.
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500ns,
b2LHfl27
0013Sbl
74LS18P
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so 54 t
Abstract: 74LS299 APPLICATIONS
Text: M MOTOROLA SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The S N 54/74LS 323 is an 8-Bit Universal S hift/S torage Register with 3-state outputs. Its function is sim ilar to the SN 54/74LS 299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are
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SN54/74LS323
54/74LS
SN54/74LS323
so 54 t
74LS299 APPLICATIONS
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74ls290
Abstract: IC 74ls290
Text: MOTOROLA SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The SN 54/74LS 290 and S N 54/74LS 293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two sec tion and either a divide-by-five LS290 or divide-by-eight (LS293) section
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SN54/74LS290
SN54/74LS293
54/74LS
LS290)
LS293)
odulo-16
LS290
74ls290
IC 74ls290
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74ls48 PIN OUT
Abstract: No abstract text available
Text: <8> M OTOROLA D E S C R IP T IO N — The S N 54LS /74LS 48 and S N 54LS /74LS 49 are BCD to 7-Segm ent Decoders consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. The LS49 offers active HIGH opencollector outputs for current-sourcing applications to drive logic circuits
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/74LS
74ls48 PIN OUT
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Untitled
Abstract: No abstract text available
Text: g MOTOROLA SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER The S N 54/74LS 290 and S N 54/74LS 293 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two sec tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
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SN54/74LS290
SN54/74LS293
54/74LS
LS290)
LS293)
odulo-16
LS290
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DL093D
Abstract: scans-048 74LS93N DSAGER00017 DL090D plh-1648
Text: m f f l k [ n > S e l e N t e n o r i i S » DL 090 D DL 093 D Internationale Vergleichstypen: SN 74LS 90 N SN 74LS 93 N S chaltkreise in Low -P ower-Schottky-Teehnologie DL 090 D Dezimalzähler DL 093 D 4 Bit-Binärzähler V orläufige technische Daten
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SN74LS604
Abstract: No abstract text available
Text: SN54LS604, SN54LS606, SN54LS607, SN74LS604, SN74LS606, SN74LS607 OCTAL 2-INPUT MULTIPLEXED LATCHES D254-5, JULY 1979-REVISED MARCH 1988 T IM 9 9 6 0 4 , T IM 9 9 6 0 6 , T IM 9 9 6 0 7 SN 54LS 604, SN 54LS 606, SN 54LS607 . . JO PACKAGE SN 74LS 604, SN 74LS 606. SN 74LS607 . . . JD OR N PACKAGE
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SN54LS604,
SN54LS606,
SN54LS607,
SN74LS604,
SN74LS606,
SN74LS607
D254-5,
1979-REVISED
LS606)
CLS607)
SN74LS604
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74Ls79
Abstract: No abstract text available
Text: M MOTOROLA SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS The S N 54/74LS 795 thru S N 54/74LS 798 device types provide a second source for the 7 1 /8 1 LS95 thru 71 /81LS 98 series. These devices are octal low power Schottky versions of the 70/8095 thru 70/8098 3-STATE Hex
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SN54/74LS795
SN54/74LS796
SN54/74LS797
SN54/74LS798
54/74LS
/81LS
LS795
LS797
LS796
74Ls79
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pin DIAGRAM OF IC 74ls75
Abstract: 74LS75 logic Ic 74
Text: M M O T O R O L A SN54/74LS75 SN54/74LS77 4-BIT D LATCH The TTL/MSI S N 54/74LS 75 and S N 54/74LS 77 are latches used as tem porary storage for binary information between processing units and input/out put or indicator units. Information present at a data (D) input is transferred to
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54/74LS
16-pin
pin DIAGRAM OF IC 74ls75
74LS75
logic Ic 74
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mitsubishi air conditioning
Abstract: 20-PIN M74LS51P Scans-000 74ls51p
Text: MITSUBISHI LSTTLs M 74LS 51P DUAL 2 -W ID E 2 -IN P U T /3 -IN P U T AND -O R -IN VER T GATE DESCRIPTION The M 74LS 51P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing dual 2-wide 2-in p u t/3 -in p u t A N D -O R -IN V E R T
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M74LS51P
M74LS51P
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
mitsubishi air conditioning
Scans-000
74ls51p
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