74HC00 NOT GATE Search Results

Contextual Info: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 6 — 14 December 2011 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC00

Abstract: tPHL 74hc00 74hc00t CI 74HC00 74hc00 and gates 74hc00 tphl tplh 14 pin 74HC00 74hc00 on 74HC00 ordering information cmos 74hc00
Contextual Info: 74HC00 QUADRUPLE 2-INPUT NAND GATES Description Pin Assignments The 74HC00 provides provides four independent 2-input NAND gates with standard push-pull outputs. The device is designed for operation with a power supply range of 2.0V to 6.0V. The gates perform the Boolean function:

74HC00 NOT GATE

Abstract: 74HC00 74HCT00 TTL 74HC00 74HC00 national semiconductor 74HC00 B1 74HCT00N 74HC00DB 74HC00N 74HCT00D
Contextual Info: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 5 — 25 November 2010 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC00

Abstract: 74HCT00 74HC00N 74hc00 tphl tplh 74HC00DB 74HC00PW 74HC00 B1 tPHL 74hc00 74HCT00DB 74HC00N function table
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supersedes data of 1997 Aug 26 2003 Jun 25 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A

74hc00n

Abstract: 74hct00 CI 74hct00 74HC00DB 74HC00PW 74HC00 14 pin 74HC00 74HC00 B1 74HC00 ordering information 74HCT00DB
Contextual Info: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 6 — 14 December 2011 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74hc00

Abstract: TTL 74HC00 74HCT00 74HCT00N 74HC00DB 74HCT00D 74HCT00DB 74HC00 B1 74HC00N function table 74HC00 ordering information
Contextual Info: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 04 — 11 January 2010 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC00

Abstract: 74hc00 datasheet 74HC00N 74HCT00 tPHL 74hc00 74hct00n 74HCT00D 74hc00 gate TTL 74HC00 74HC00DB
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supersedes data of 1997 Aug 26 2003 Jun 30 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A

tPHL 74hc00

Abstract: 74HC00 TTL 74HC00 74HCT00 74HC00D 74HC00DB 74HC00N 74HCT00D 74HCT00DB 74HCT00N
Contextual Info: Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL . They are specified in compliance with

Contextual Info: 74HC00 Quad 2-Input NAND Gate High-Performance Silicon-Gate CMOS The 74HC00 is identical in pinout to the LS00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. http://onsemi.com Features

TTL 74HC00

Abstract: 74HC00 74HC00N 74HCT00 74HC00 B1 74HC00 quad CMOS nand gate CI 74HC00 74HCT00D 74HCT00N 74HC00D
Contextual Info: Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES DESCRIPTION • Complies with JEDEC standard no. 8-1A The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL . They are specified in compliance with

Contextual Info: 74HC00 Quad 2−Input NAND Gate High−Performance Silicon−Gate CMOS The 74HC00 is identical in pinout to the LS00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. http://onsemi.com

HC00G

Abstract: 74hc00 equivalent TTL 74HC00 74HC00 B1 74hc00 and gates 74HC00 74HC00DR2G 74hc00 on 74HC00D cmos 74hc00
Contextual Info: 74HC00 Quad 2-Input NAND Gate High-Performance Silicon-Gate CMOS The 74HC00 is identical in pinout to the LS00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. http://onsemi.com Features

IC 74HC00

Abstract: tPHL 74hc00 5V 74HC00 74HC00 74hc00 equivalent 74HC00 B1 74hc00 tphl tplh SGS-Thomson 74hc00
Contextual Info: M54HC00 M74HC00 S G S -T tfO M S O N QUAD 2-INPUT NAND GATE HIGH SPEED tpD = 8 ns TYP. at V c c = 5V LOW POWER DISSIPATION Ice = 1 (MAX.) at T a = 25°C HIGH NOISE IMMUNITY V n ih = V n i L = 28% V CC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS vu 1 B1

5-Volt Data Bus

Abstract: 8096 microcontroller temperature control of 8096 3volt inverter 74HC00 74HC00 CMOS 1N4370A 74HC 5V 74HC00
Contextual Info: Interfacing Atmel LV/BV EPROMs on a Mixed 3-volt/5-volt Data Bus EPROM Introduction Interfacing Atmel Corporation’s low voltage LV/BV EPROMs on a common data bus with standard 5-volt devices can be achieved with relative ease if a few simple guidelines are followed. By

74HC00

Abstract: ixdp630 IXDP630 application note 3 phase ups schematic diagram make three phase ups schematic diagram IXDB4410 74HC00-1 IXBD4411PI 74hc00 oscillator circuit IXDD414
Contextual Info: EVBD4400 HALF BRIDGE DRIVER Evaluation Board Features Introduction • High to low side isolation of 1000V • Common-mode dv/dt immunity of greater than 50V/nanosecond • On-chip generated negative gate drive • Overcurrent protection by means of desaturation

TX02-4400PI

Contextual Info: EVBD4400 HALF BRIDGE DRIVER Evaluation Board Features Introduction • High to low side isolation of 1000V • Common-mode dv/dt immunity of greater than 50V/nanosecond • On-chip generated negative gate drive • Overcurrent protection by means of desaturation

IC 74HC00

Abstract: 74hc00 b1 tPHL 74hc00 M74HC00B1N 74HCoo 74HC00 74hc00 equivalent 74hc00 tphl tplh 74LS00 Electrical and Switching characteristics SGS-Thomson 74hc00
Contextual Info: SGS -THOMSON M 54H C 00 M 74HC 00 0 03©i[Li{gT03©[iM0 êS QUAD 2-INPUT NAND GATE HIGH SPEED tpD = 8 ns (TYP. at V c c = 5V LOW POW ER DISSiPATION Ic e = 1 /*A (MAX.) at T a = 2 5 °C HIGH NOISE IM M UN ITY V n ih = V n i l = 280/o V CC (MIN.) O UTPU T DRIVE CAPABILITY

8096 microcontroller

Abstract: 74HC00 CMOS 74HC00 temperature control of 8096 74HCoo
Contextual Info: CMOS EPROM Interfacing Atmel LV/BV EPROMs on a Mixed 3-Volt/5-Volt Data Bus Introduction Interfacing Atmel Corporation's low volt­ age LV/BV EPROMs on a common data bus with standard 5-volt devices can be achieved with relative ease if a few simple guidelines are followed. By

74HCoo

Abstract: IN4370A lN746A IN4370 8096 microcontroller IN746A temperature control of 8096 in746 IN437
Contextual Info: CMOS EPROM Interfacing Atmel LV EPROMs on a Mixed Three-Volt/Five-Volt Data Bus Introduction Interfacing Atmel Corporation’s low voltage LV EPROM s on a common data bus with standard five-volt devices can be achieved with relative ease if a few simple

ma 8127

Abstract: 74hc00 gate 74HC00 national semiconductor Difference between LS, HC, HCT devices 74c SERIES cmos logic data application circuits of ic 74HC74 CD4000 74hc74s f 8127 74HC00 SERIES DATA
Contextual Info: National Semiconductor Application Note 375 Larry Wakeman November 1984 To maximize the benefits of high-speed CMOS you must cope with environmental interactions and component limitations Especially important are system noise decoupling and both transient and steady-state level control

Difference between LS, HC, HCT devices

Abstract: 74hc00 gate 74hc00 equivalent 74hc00 datasheet 74hc00 fairchild 74HC74 application note 74HC00 74hc00 and gates 74HC74S IC 74HC00
Contextual Info: Fairchild Semiconductor Application Note 375 October 1984 To maximize the benefits of high-speed CMOS, you must cope with environmental interactions and component limitations. Especially important are system noise decoupling and both transient and steady-state level control.

82c51

Abstract: 74HC00 74hc xor gate 74HCxx 74HC191
Contextual Info: SINGLE-CHIP SYSTEMS CPU CORES Gate Array with Built-in CPU Core SFASIC In a d d itio n to c o n v e n tio n a l c e ll- b a s e d s in g le - c h ip s y s te m s , S h a rp a ls o o ffe rs s h o rt tu rn a ro u n d tim e ga te 82CXX series macrocell a rra y s w ith a b u ilt-in C P U c o re . In o rd e r to m e e t e ve n

82C51 NEC

Abstract: 82c51 NEC 82c55 z80 microprocessor memory management 74HC00 74hc xor gate NEC uPD780-1 Z80
Contextual Info: SINGLE-CHIP SYSTEMS, CPU CORES In addition to conventional cell-based single-chip systems, Sharp also offers short turnaround time gate arrays with a built-in CPU core. In order to meet even wider market requirements, Sharp provides not only the field-proven Z80, but also the V20HL/V30HL, a high­

54HC390

Abstract: 54HC139 for 74hc04 CD4000 MM74HC 74hc164 74hc00 equivalent 74HC00 25c74 FAIRCHILD MM74HC
Contextual Info: Fairchild Semiconductor Application Note 317 April 1989 When deciding what circuits to use for a design, speed is most often a very important criteria. MM74HC is intended to offer the same basic speed performance as low power Schottky TTL while giving the designer the low power and