74LVX373 Search Results

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373SJ M20D MTC20
Contextual Info: 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH.

74LVX373

Contextual Info: 74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

74LVX373

Abstract: 74LVX373M 74LVX373T
Contextual Info: 74LVX373  LOW VOLTAGE OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.8 ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V

Contextual Info: 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH.

Contextual Info: S E M I C O N D U C T O R -n 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH.

74LVX373

Abstract: semikron semipont 2 skch 40/12 74LVX373M 74LVX373T
Contextual Info: 74LVX373  LOW VOLTAGE OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.8 ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373SJ M20D MTC20
Contextual Info: 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches w ith 3-STATE outputs for bus organized system applications. The latches appear transparent to the d ata w hen Latch Enable LE is HIGH.

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373MTCX 74LVX373MX 74LVX373SJ 74LVX373SJX M20D LVX373
Contextual Info: 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs General Description Features The LVX373 consists of eight latches with TRI-STATE outputs for bus organized system applications The latches appear transparent to the data when Latch Enable LE is

74LVX373

Abstract: 74LVX373M 74LVX373MTR 74LVX373TTR
Contextual Info: 74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373SJ M20D MS-013 MTC20 JEDEC J-STD-020B
Contextual Info: Revised April 2005 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH.

MTC20

Abstract: 74LVX373 74LVX373M 74LVX373MTC 74LVX373SJ M20D MS-013
Contextual Info: Revised March 1999 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH.

74LVX373

Abstract: 74LVX373M 74LVX373MTR 74LVX373TTR
Contextual Info: 74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

Contextual Info: 74LVX373 LOW VOLTAGE OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS . . . . . . . . HIGH SPEED: tpD = 5.8 ns (TYP.) at Vcc = 3.3V 5VTOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: V il = 0.8V, V ih = 2V at Vcc = 3V LOW POWER DISSIPATION:

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373MTCX 74LVX373MX 74LVX373SJ 74LVX373SJX
Contextual Info: LVX373 National Semiconductor 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs General Description Features The LVX373 consists of eight latches with TRI-STATE out­ puts for bus organized system applications. The latches ap­ pear transparent to the data when Latch Enable LE is

74LVX373

Abstract: 74LVX373MTR 74LVX373TTR
Contextual Info: 74LVX373 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH 3-STATE NON INV. WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V

LVX373

Contextual Info: LVX373 EH ÆÆ National Semiconductor 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs General Description Features The LVX373 consists of eight latches with TRI-STATE out­ puts for bus organized system applications. The latches ap­

LVX373

Abstract: 74LVX373 74LVX373M 74LVX373MTC 74LVX373SJ M20D MS-013 MTC20
Contextual Info: Revised September 2003 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH.

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

74LVT JK Flip Flop

Abstract: led driver SOT23 6pin lcx244 MOTOROLA lcx 4245 LCX244 quad single supply 50 Ohm Line Drivers diode sj Fairchild Power Switch package to 220 p5 MAX 16841 On semiconductor LCX 574 PA
Contextual Info: 1 Chapter 1 Introduction to Low-Voltage Logic Chapter C R O S S V O L T Parts & Availability 17 Packaging Options 37 Low-Voltage Logic Cross Reference 49 Glossary 57 Fairchild Low-Voltage Logic Reference Guide Chapter Chapter Glossary  Introduction to Low-Voltage Logic

74LVX373

Abstract: 74LVX373M 74LVX373MTC 74LVX373SJ M20D MS-013 MTC20
Contextual Info: Revised March 1999 SEMICQNDUCTGRTM General Description The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data satisfying the input timing

Contextual Info: ALPHANUMERICAL INDEX LCX FAMILY Type Number Function Package Page Number 51 74LCX00 Quad 2-Input NAND Gate with 5V Tolerant Input TSS0P/S014 74LCX02 Quad 2-Input NOR Gate with 5V Tolerant Input TSS0P/S014 57 74LCX04 Hex Inverter with 5V Tolerant Input TSS0P/S014

Contextual Info: Section 8 LV X Family * Section 8 Contents LVX Family Features. 74LVX00 Low Voltage Quad 2-Input NAND G a t e .

FQPF*7N65C APPLICATIONS

Abstract: bc548 spice model bf494 spice model spice model bf199 LM3171 BC517 spice model bc547 spice model BF494 spice MOC3043-M spice model SPICE model BC237
Contextual Info: Fairchild PSG.book Page i Wednesday, July 28, 2004 11:12 AM Fairchild Semiconductor Product Catalog Rev. 1 Analog & Mixed Signal Discrete Power Interface & Logic Microcontrollers Optoelectronics RF Power Front Matter.fm Page ii Monday, August 2, 2004 10:09 AM

Contextual Info: SEMICONDUCTOR June 1993 Revised March 1999 TM output is in the high im pedance state. The inputs tolerate up to 7V allowing interface of 5V system s to 3V system s. General Description The LVX373 consists of eight latches with 3-STATE outputs fo r bus organized system applications. The latches a ppear