74LS7S Search Results

74LS7S

Abstract: DN74LS73 MA161
Contextual Info: DN74LS73 LS TTL DN74LS Series DN74LS73 biv '74LS7s Dual J-K F lip -F lop s with Reset) P-1 • Description DN74LS73 contains tw o negative-edge triggered J-K flip-flop circuit, each w ith independent clock CP, J, K, and directcoupled reset input terminals.

Contextual Info: LS TTL DN74LS Series DN74LS73 bivJ 74LS7S DN74LS73 Dual J-K F lip -F lop s with Reset • Description P-1 DN74LS73 contains two negative-edge triggered J-K flip-flop circuit, each with independent clock CP, J, K, and directcoupled reset input terminals.

SN74LS375

Abstract: SN54LS375 SN54LS75 4 bit bistable latch device t11j
Contextual Info: S N54LS375, S N 74LS 3 75 4 BIT B IS T A B LE LA T C H ES SDLS16G • OCTOBER 1 9 7 6 - S N 54LS375 J OH W PACKAGE S N 74LS375 . . . D OR N PACKAGE Supply Voltage and Ground on Corner Pins To S im plify P-C Board Layout TOP VIEW 12 C 1 U , 6 IQ E 7 1Q C 3