74HC11 |
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Philips Semiconductors
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Triple 3-Input AND Gate |
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Original |
PDF
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74HC112 |
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Philips Semiconductors
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Negative-edge trigger |
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Original |
PDF
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74HC112D |
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Philips Semiconductors
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dual JK flip-flop with set and reset negative-edge trigger |
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Original |
PDF
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74HC112D |
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Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
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Historical |
PDF
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74HC112D,652 |
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NXP Semiconductors
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC |
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Original |
PDF
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74HC112D,653 |
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NXP Semiconductors
|
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC |
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Original |
PDF
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74HC112DB |
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Philips Semiconductors
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dual JK flip-flop with set and reset negative-edge trigger |
|
Original |
PDF
|
74HC112DB |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
|
74HC112DB,112 |
|
NXP Semiconductors
|
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Tube |
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Original |
PDF
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74HC112DB,118 |
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NXP Semiconductors
|
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" |
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Original |
PDF
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74HC112DB-T |
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NXP Semiconductors
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V |
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Original |
PDF
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74HC112DB-T |
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Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
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74HC112D-T |
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NXP Semiconductors
|
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V |
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Original |
PDF
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74HC112D-T |
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Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
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74HC112N |
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Philips Semiconductors
|
dual JK flip-flop with set and reset negative-edge trigger |
|
Original |
PDF
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74HC112N |
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Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
|
74HC112N,652 |
|
NXP Semiconductors
|
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC |
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Original |
PDF
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74HC112PW |
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Philips Semiconductors
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dual JK flip-flop with set and reset negative-edge trigger |
|
Original |
PDF
|
74HC112PW |
|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
|
Historical |
PDF
|
74HC112PW,112 |
|
NXP Semiconductors
|
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Tube |
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Original |
PDF
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