74ALS02D Search Results

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

Contextual Info: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir­ cuit consisting of four 2-input positive-logic NOR buffer

J 5027 R

Abstract: BEM 6K
Contextual Info: MIT SUBISH I íDGTL L O G I C } T I d ËT| ^5^027 ~JZ.SZt~3/ G0127SS □ MITSUBISHI ALSTTLs M 74A L S 1621A P I 62 49 8 2 7 M I T S U B I S H T T D G T L T o G r ^ ~ 910 12755 D OCTAL BUS TRANSCEIVER W ITH OPEN COLLECTOR OUTPUT NONINVERTED) DESCRIPTION

m74als

Abstract: M74ALS109AP 74ALS640
Contextual Info: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The M74ALS109AP is a semiconductor Integrated circuit

M74ALS1032AP

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1 0 3 2 AP M I T S U B I S H I - C D G T L L O G I C } T I D È I ” L ^ M ^ ñ S ? 1 2 7 5 fi QUADRUPLE 2-IN P U T POSITIVE OR BUFFER _ DESCRIPTION _ _ _ _ PIN CONFIGURATION TOP VIEW The M74ALS1032AP is a semiconductor integrated cir­

74ALS02D

Abstract: 74ALS 74ALS02 74ALS02N
Contextual Info: INTEGRATED CIRCUITS 74ALS02 Quad 2-Input NOR gate Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Quad 2-input NOR gate 74ALS02 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL

c 2274

Contextual Info: '7 ' '0 7 -0 5 * MITSUBISHI ALSTTLs OCTAL D -TY P E EDGE-TRIGGERED FLIP-FLO P W IT H 3-S TA TE O U TPU T N O N IN V E R TE D . Ä > a 6249827 M IT S U B IS H I (D G TL L O G IC ) DESCRIPTION consisting o f eight D-type positive edge-triggered flipflop circuits w ith 3-state noninverted output and is pro­

74ALS273P

Abstract: M74ALS273P
Contextual Info: MITSUBISHI -CDGTL LOGIC} TI D e B bSMTñE? DDIHSDI 5 MITSUBISHI ALSTTLs M 74A LS273P T z- / ù > ~ o y - < o s ' OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH RESET 9 1D 12501 6249827 MITSUBISHI ÍDGTL LOgT c T DESCRIPTION PIN CONFIGURATION TOP VIEW

74als520

Abstract: dd127
Contextual Info: MITSUBISHI -CDGTL LOGIC* TI ^F|t.SMTñ27 0015543 7 J ~ MITSUBISHI ALSTTLs & M 74A LS519P > ^ vA" 0\ 7 ^ .V «" / 5 e / ' 7 8-BIT MAGNITUDE COMPARATOR WITH OPEN COLLECTOR OUTPUT 9 1D 12543 6249827 MITSUBISHI DGTL LOGIC DESCRIPTION Th e M 7 4 A L S 5 1 9 P is a sem iconductor integ rated circuit

74ALS643

Contextual Info: MITSUBISHI ALSTTLs M 74A L S 643A P MITSUBISHI -CDGTL LOGIC} TI D E I bSMTÖE? 0012t,4b b OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M74ALS643AP is a semiconductor integrated circuit consisting of eight bus transm itter/receiver circuits with

QAA11

Contextual Info: MITSUBISHI -CDGTL LOGICI TI . I DE I DO 1 5 7 SA MITSUBISHI A LS T T Ls M74ALS1622AP _ 6249827 MITSUBISHI b DGTL L O GI C 91D 12758 D OCTAL BUS TR A N SC EIVER W IT H OPEN COLLECTOR O U T P U T (IN V E R T E D ) -T 'S a DESCRIPTION PIN CONFIGURATION (TOP VIEW)

74ALS640

Contextual Info: MITSUBISHI íDGTL LOGICI TI D È I b24TñE7 0 0 1 2 4 ^ 5 □ MITSUBISHI ALSTTLs M 74A LS257P * 0 0 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT 624 98 27 MITSUBISHI 9 1D 12495 CDGTL LOGIC DESCRIPTION PIN CONFIGURATION TOP VIEW)

74als520

Contextual Info: MITSUBISHI <DGTL LOGIC} TI DE|t2»nfla7 DQ1ES40 1 |~ MITSUBISHI ALSTTLs M74ALS518P « g * oeC ^T xo^ „v a i'0’»«'*]?*>xä»c' «S'ot^uv« * * 7 ^ 5 V 7 8 -B IT MAGNITUDE COMPARATOR W ITH OPEN COLLECTOR OUTPUT 6249827 MITSUBISHI <DGTL LOGIC DESCRIPTION

74ALS620AP

Contextual Info: MITSUBISHI ALSTTLs M 74A L S 6 20A P I MITSUBISHI -CDGTL LOGIC} TI DeT I 324^527 Dim2b 14 4 | OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT (INVERTED DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS620AP is a semiconductor integrated circuit consisting of eight bus transm itter/receiver circuits with

Contextual Info: MITSUBISHI O G T L 3>EI tiSM^ñS? o o i a s s s 3^f~ LOGIC} MITSUBISHI ALSTTLs M 74A LS533P T = - Ÿ 6 -0 7 -o s * OCTAL D-TYPE TRANSPARENT LATCH W ITH 3-STATE OUTPUT INVERTED 6 2 4 9 82 7 M ITSUBISHI (DGTL LOGIC) DESCRIPTION 9 1D 12 555 D PIN CONFIGURATION (TOP VIEW)

M74ALS02P

Abstract: 74ALS640
Contextual Info: MITSUBISHI ÍDGTL LOGIO TI 1>ËJ £,241027 0012321 S ï~ MITSUBISHI ALSTTLs M 74A LS 02P 6249827 MITSUBISHI {D G T L LOGIC “ 91° 1 2329 D QUADRUPLE 2 -IN P U T P O S ITIV E NOR GATE DESCRIPTION The M74ALS02P is a semiconductor integrated circuit consisting of four 2-input positive-logic NOR gates,

D0127D

Abstract: D0127
Contextual Info: MITSUBISHI ALSTTLs M74ALS878AP V " DUAL 4 -B IT D-TYPE EDGE-TRIGGERED FLIP-FLOP W ITH 3-STATE OUTPUT AND SYNCHRONOUS RESET NONINVERTED $249827 MITSUBISHI ESET INPUT DATA INPUTS • IQ 1 * 1Û 1 1D2 - 1 I D 2 102 23 1 Q2 1D3 -H ID 3 IQ 3 20) 1 Q3 ID 4 -»[¡6

Contextual Info: MITSUBISHI -CDGTL LOGIC} =11 "D È I ^ 2 4 ^ 2 7 □□12 3t .5 "i • ” MITSUBISHI ALSTTLs M 74A LS 37A P 6249827 MITSUBISHI {D G T L I LOGICI" 91° 123 65 D QUADRUPLE 2-IN P U T POSITIVE NAND BUFFER DESCRIPTION PIN CONFIGURATION TOP VIEW Th e M 7 4A L S 37A P is a se m ic o n d u c to r in teg rated circu it

M74ALS74AP

Contextual Info: MITSUBISHI -CDGTL LOGIC} Ï Ë J QQ12371 4 f MITSUBISHI ALSTTLs _ _ _ _ M 7 4 A L S 7 4 A P 6 2 4 9 8 2 7 M I T S U B I S H I _CDQTL L O GI C 91D 12371 D DUAL D-TYPE PO SITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T~ Vfa - û 7 ~ û S

Contextual Info: Philips Sem iconductors Product specification Quad 2-input NOR gate 74ALS02 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 74ALS02 4.0ns 1,0mA PIN CONFIGURATION ORDERING INFORMATION O RDER CODE CO M M E R C IA L RANGE V cc = 5V ±10%, Tamb = ° ° c to +70°C

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 2 P p W 'T ^ S '^ - 3 / 50"‘ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT NONINVERTED N °"c< 6249827 MITSUBISHI ÍDGTL DESCRIPTION The M74ALS652P is a semiconductor Integrated circuit consisting of eight bus transceiver/registers with 3-state

M74ALS00AP

Contextual Info: MITSUBISHI -CDGTL L O G I O D E I =11 b E M T B B V □ □ 1 2 3 2 7 1 | MITSUBISHI ALSTTLs M 74A LS00A P 6249827 MITSUBISHI ÖDGTL LOGIC 91D 12327 D QUADRUPLE 2-IN P U T POSITIVE NAND GATE 7 = y j - / r DESCRIPTION T h e M 7 4A L S 00A P is a sem ic o n d u c to r in teg rated circu it

M74ALS10AP

Contextual Info: MITSUBISHI ÍDGTL LOGIC} TI D E I b E M T f lE ? 0 0 1 2 3 4 1 t. I M IT S U B IS H F a LSTTL s M 74A LS10A P 6249827 MITSUBISHI {D G T L LOGIC 910 12341 D TRIPLE 3-IN P U T POSITIVE NAND GATE T-Y3-/S* PIN CONFIGURATION TOP VIEW) DESCRIPTION The M74ALS10AP is a semiconductor integrated circuit