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Texas Instruments 74AC11010N IC,LOGIC GATE,3 3-INPUT NAND,AC-CMOS,DIP,16PIN,PLASTIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components	74AC11010N		174			1 $0.36 10 $0.36 100 $0.36 1000 $0.36 10000 $0.36	Buy Now
Vyrian	74AC11010N		404			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Signetics 74AC11010N IC,LOGIC GATE,3 3-INPUT NAND,AC-CMOS,DIP,16PIN,PLASTIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components	74AC11010N		10			1 $0.36 10 $0.36 100 $0.36 1000 $0.36 10000 $0.36	Buy Now
Texas Instruments 74AC11010D INSTOCK
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Chip 1 Exchange	74AC11010D		1,000			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Vyrian	74AC11010D		418			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74AC11010D Peripheral ICs
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	SN74AC11010D		1,294			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SN74AC11010DR Peripheral ICs
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	SN74AC11010DR		989			1 - 10 - 100 - 1000 - 10000 -	Get Quote

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74AC11010 Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
74AC11010		Texas Instruments	TRIPLE 3-INPUT POSITIVE-NAND GATES		Original	PDF
74AC11010		Texas Instruments	TRIPLE 3-INPUT POSITIVE-NAND GATES		Original	PDF
74AC11010D		Texas Instruments	TRIPLE 3-INPUT POSITIVE-NAND GATE		Original	PDF
74AC11010D		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF
74AC11010DR		Texas Instruments	Triple 3-Input Positive-NAND Gates		Original	PDF
74AC11010N		Texas Instruments	TRIPLE 3-INPUT POSITIVE-NAND GATE		Original	PDF
74AC11010N		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.		Historical	PDF

74AC11010 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
54AC11010 Abstract: 74AC11010 Contextual Info: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCLS057 – MAY 1987 – REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations	Original	54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil 54AC11010 74AC11010	PDF
54AC11010 Abstract: 74AC11010 Contextual Info: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCLS057 – MAY 1987 – REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations	Original	54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil 54AC11010 74AC11010	PDF
Contextual Info: 54AC11010, 74AC11010 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES ăą SCLS057 − MAY 1987 − REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations	Original	54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil	PDF
54AC11010 Abstract: 74AC11010 Contextual Info: 54AC11010, 74AC11010 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES ăą SCLS057 − MAY 1987 − REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations	Original	54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil 54AC11010 74AC11010	PDF
S2-34 Contextual Info: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES TI0048— D2957, M AY 1987—R EVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11010 . . . J PACKAGE 74AC11010 . . . 0 OR N PACKAGE TOP VIEW • Center-PIn Vq c and GND Configurations to	OCR Scan	54AC11010, 74AC11010 TI0048-- D2957, 1987--R 500-mA 300-mil 54AC11010 S2-34	PDF
54AC11010 Abstract: 74AC11010 D2957 Contextual Info: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES TI0048— D2957, MAY 1987—REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11010 . . . J PACKAGE 74AC11010 . . . D O R N PACKAGE TOP VIEW Center-Pin V q C and GND Configurations to	OCR Scan	54AC11010, 74AC11010 TI0048â D2957, 500-mA 300-mil 54AC11010 74AC11010 D2957	PDF
Contextual Info: 54AC11010,74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES D2957, MAY 1987 - REVISED APRIL 1993 • ■ * Flow-Through Architecture Optimizes PCB Layout I I • Center-Pin Vqq and GND Configurations Minimize High-Speed Switching Noise \| • EPIC'" Enhanced-Performance Implanted	OCR Scan	54AC11010 74AC11010 D2957, 500-mA 300-mil 54AC11010	PDF
Contextual Info: 54AC11010,74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES D2957, MAY 1987 - REVISED APRIL 1983 Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise EP IC “ Enhanced-Performance Implanted CMOS 1-\|j.m Process	OCR Scan	54AC11010 74AC11010 D2957, 500-mA 300-mll	PDF