74193 A Search Results

ic 74193

Contextual Info: Sem iconductor DM54192/DM74192, DM 54193/DM 74193 Synchronous Up/Down Counters w ith Dual Clock General Description These c irc u its are synchronous up/down counters; the 192 c irc u it is a BCD counter and the 193 is a 4-bit binary counter. Synchronous operation is provided by having all

programmable binary counter 74193

Abstract: 74193PC 74193 state diagram 74LS193 pin data 74LS193PC 74193 74ls193p 74193 state diagram up counter 74LS193 74LS193B
Contextual Info: 193 CONNECTIO N DIAGRAM PINOUT A 54/74193 à 9X 5 4 L S /7 4 L S 1 9 3 ô /ô -E Oi UP/DOW N BINARY COUNTER H ] V cc njpo [T Ï71 MR O o (T (With Separate Up/down Clocks T 5 ]tc d CPd E [I [F Til PL 03 [7 33p 2 CPU DESCRIPTION — The ’193 is an up/dow n m odulo-16 binary counter. Sep­

Contextual Info: INTEGRATED CIR CU IT S 74193 276-1820 TTL SYN CH RO N O U S U P/D O W N COUNTER WITH DUAL CLO CK G ENERAL DESCRIPTION T h e 71193 <s a 4 -hit b i n a r y i.tmnhM' S y n c h r o n o u s o p e r a t i o n js »>rciv by h a v i n g all f l i p fl ops c l o c k e d s i m u i t a n e o u s l y , so t hai the o u t p u t s c h a n g e

74192

Abstract: 74193 NAFI 74LSI92 BCD counter 74LS193 74193 A 74192 counter
Contextual Info: — 152 — 74192 Presettable Synchronous Up/Down BC D Counter dual clock, with clear ' NPVTS *cc * OUTP UTS I NP UT S ^ ^ •tmwow c p 1 A A C L C A H K M IR O W C A f A A I Or On XX DAT* 0B Q. COUN I COUNT G ND o i \ i - v Y m W - £ T ' v - r r < j > U O > ? ( &9 i J A * )

74LS190 pins

Abstract: 74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins Synchronous 74163 74LS161 74160 74LS162 74LS191 pins
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L-T T L D121 54/7490A, 54LS/74LS90 D122 54/7492, 74LS92 D123 S4/74293, 54LS/74LS293 6 7 141 Vcc = Pin 5 GND = Pin 10 N C = Pin 4,13 - Vcc = Pin 5 GND = Pin 10 N C = 2, 3, 4, 13 D124 S4/7493A, 54LS/74LS93 D125 54/74176, 54/74177,

Contextual Info: LS7083 LS7084 Encoder to Counter Interface Chips V ^ T ech n ical Data, rev. 1.08, June 1994 Features: Quadrature Clock Converters • X4 or XI resolution multiplication • TTL and CMOS compatible • Low power micro-amps • 8-pin DIP package • No external clocks required

Contextual Info: LS7183 / LS7184 Encoder to Counter Interface Chips Description: Features: The LS7183 and LS7184 provide an interface between industry standard A and B quadrature incremental encoder outputs to standard up/down counters. The LS7183 outputs can connect directly to the up and

CI 7473

Abstract: counter with 7473 7490 Decade Counter 7476 up down counter 7476 counter ci 74192 decade counter 7492 74122 Retriggerable Monostable Multivibrator ci 7476 7490 counter
Contextual Info: BIPOLAR DIGITAL ICs continued :lip-flops T 7472/5472 T 7473/5473 T 7474/5474 T 7476/5476 T 74107/54107 T 74121/54121 T 74122/54122 T 74123/54123 Jther functions T 7441 A/5441 A T 7442/5442 T 7443/5443 T 7444/5444 T 7475/5475 T 7481/5481 T 7483/5483 T 7484/5484

ic 74193

Abstract: AD9686 of IC 74193 AD9500 AD96685 AN-261 MC10131 74193 pin configuration A09500 pin diagram of counter ic 74193
Contextual Info: AN-261 APPLICATION NOTE ANALOG ► DEVICES ONE TECHNOLOGY WAY • P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700 Programmable-Delay ICs Control System Timing by Craven Hilton and Jeff Barrow Low cost, low power, and sm all package size extend the application o f digital-totime converters in system tim ing applica­

7404 dip

Abstract: 7493 4 bit binary counter 4 nand dip 16 74122 Retriggerable Monostable Multivibrator Noise immunity of 7408 7476 counter CI 7405 Noise immunity of 7486 decade counter 7492 7492 binary counter
Contextual Info: BIPOLAR DIGITAL ICs continued TYPE T T L - T 7 4 , T 54 series" z o 1Q. C TJ a. 5 B O- OC O I=3 O z < ÜJ ID < u < Q- C/3 LU O Gates T 7400/5400 Quad 2-input N A N D 10 40 10 D IP H,P T 7401/5401 Quad 2-input open-collector N A N D 10 40 10 D IP H,P T 7402/5402

Truth Table 74192

Abstract: Truth Table 74193 74193 truth table TC40193BP TC40192
Contextual Info: TC40192BP,TC40193BP i;æ§NDaTNAoLLaFcGRATEDCRCUT TC40192BP PRE SETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRE SETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) TC40192BP/TC40193BP is synchronous 4-bit up/down counter. The RESET input is active at "H" level, and the

Truth Table 74192

Abstract: Truth Table 74193 TC40192 TC40192BP 74193 truth table TC40193BP
Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual'Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) TC40192BP/TC40193BP is a synchronous 4-bit up/down counter. The RESET input is active at "H" level, and the

74193 truth table

Abstract: Truth Table 74193 TTL74192 TC40H192P ttl74 74193 pin assignment TC40H
Contextual Info: TOSHIBA INTEGRATED CIRCUIT TECHNICAL DATA . TC40H 192P/F TC40H 193P/F C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 4 0H 1 92 SYNCHRONOUS DUAL CLOCK SYNCHRONOUS (DU AL CLOCK TC40H 19 3 BCD UP/DOWN COUNTER WITH C L E f ? 4 - B I T BIN ARY UP/DOWN COUNTER

sn 7492 ttl

Abstract: 74293 pin diagram TTL 7493A TTL 74293 7493A 74162 74LS93 74293 74LS183 74LS90
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 D122 54/7492, 74LS92 D123 S4/74293, 54LS/74LS293 6 7 141 Vcc = Pin 5 GND = Pin 10 NC = Pin 4,13 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D124 S4/7493A, 54LS/74LS93 D125 54/74176, 54/74177,

74L193

Abstract: SN74L193 SN54119 ic 74192 SN741S193 LS 7313 - S SJ74193 sn74l192 SN741S2 LS 7313 S
Contextual Info: TYPES SKS4192. SN54193, SW54L192. SN54LÎ93, SN54LS192, SN54LS193 SN74Î92, SJ74193, SH74LW2. SN74L193, SN74LS192, SN74LS193 SYNCHRONOUS 4-BÎT UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR B U L L E T I N N O . 0 1 - 8 7 7 1 1«3». O E C E M B E W 1 » 7 2 -W li V IS E D A U G U S T 1877

7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
Contextual Info: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­

TC40193BP

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40192BP,TC40193BP TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) TC40192BP/TC40193BP synchronous 4-bit up/down counter.

CI 74LS90

Abstract: ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 74LS93 TTL 74293 TTL 7493A sn 7492 ttl
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D121 54/7490A, 54LS/74LS90 D122 54/7492, 74LS92 D123 S4/74293, 54LS/74LS293 6 7 141 Vcc = Pin 5 GND = Pin 10 NC = Pin 4,13 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D124 S4/7493A, 54LS/74LS93 D125 54/74176, 54/74177,

Truth Table 74192

Abstract: pin diagram of counter ic 74193 74193 truth table ic 74192 74192 ic Truth Table 74193 of IC 74193 TC40192BPJC40193BP IC TTL 74193 TC40192BP/TC40193BP
Contextual Info: TC40192BPJC40193BP C2M 0 S DIGITAL INTEGRATED CIRCUIT SILICO N MONOLITHIC TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) T C 4 0 1 9 2 B P / T C40193BP i synchronous 4-bit up/down

MH 74141

Abstract: Tesla katalog MH74S04 MH74188 information applikation MH74S287 mikroelektronik RFT CDB404E ucy 74132 MZH 115
Contextual Info: m o N r ^ e le l- c fe n a n il- c Information Applikation ._ B|B Information Applikation Heft 26: IMPORT-IS Teil 2 i ' . • fbkj veb Halbleiterwerk frankfurt/oder Ü B d batriab im vab ko m binat mfcr m M ftrnnllt DER TECHNIK I Bezirksvorstand Frankfurt/O.

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

pin diagram of counter ic 74193

Abstract: tabla XR-1489 XR-9201CP xr494 74193 xr-9201
Contextual Info: X ' EX4R XR-9201 8-Bit Microprocessor Compatible Digital-To-Analog Converter FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-9201 is a monolithic 8-Bit /»P compatible digitalto-analog converter with differential current outputs. It contains an internal data latch, making it suitable for in­

MH1SS1

Abstract: TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L 741PC TDB0124DP tda 4100 TDA 7851 A
Contextual Info: m ö lk ^ o e le l-c te n a n il-c Information Applikation RGW Typenübersicht Vergleich Teil 2: RGW M iM U Z A U l KÉD lnrüÖC=SraO Information Applikation HEFT 50 RGW Typenübersicht + Vergleich Teil 2: RGW wob Halbleiterwerk Frankfurt /oder bt r iab im v«b kombinat mikrootektronik

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format