74 LS 193 LOGIC DIAGRAM Search Results

Contextual Info: Latticc ispLSr3448 ; ; ; Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 224 I/O — 20000 PLD Gates — 672 Registers — High Speed Global Interconnect

cd40001

Abstract: SN74AHC2G russian transistor cross-reference CD4000 SERIES BOOK NXP 74LVC1G datasheet IC CD 40106 4093 ic for bcd counter sn 16861 741HC REGULATOR IC 7804
Contextual Info: Logic Guide www.ti.com/logic 3Q 2009 2 Logic Guide 2009 ➔ Important Notice Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any

74L193

Abstract: SN74L193 SN54119 ic 74192 SN741S193 LS 7313 - S SJ74193 sn74l192 SN741S2 LS 7313 S
Contextual Info: TYPES SKS4192. SN54193, SW54L192. SN54LÎ93, SN54LS192, SN54LS193 SN74Î92, SJ74193, SH74LW2. SN74L193, SN74LS192, SN74LS193 SYNCHRONOUS 4-BÎT UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR B U L L E T I N N O . 0 1 - 8 7 7 1 1«3». O E C E M B E W 1 » 7 2 -W li V IS E D A U G U S T 1877

EPM5130

Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
Contextual Info: EPM5130 EPLD □ □ Features □ □ □ □ □ □ □ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture

8DDD

Abstract: 8282
Contextual Info: FLEX 8000 Programmable Logic Device Family J u n e 1996, ver. 8 Features. D ata S h ee t • ■ ■ ■ Table 1. FLEX 8000 Device Features Feature U sable gates Flipflops Logic array blocks LABs Logic elem ents M axim um user I/O pins JTA G B S T circuitry

Contextual Info: L>il Hilbh iT ^ irT^n r n n rssgggppr PRELIMINARY - CY82C692 Pentium hyperCache™ Chipset Data-Path/lntegrated Cache for hC-VX, hC-DX Solutions Features • Supports all 3.3V Pentium™ -class processors, AMD K5, and Cyrix M1 CPUs • Directly interfaces with CY82C691 and CY82C693 to

Contextual Info: Lattice' ispLSI 3320 | Semiconductor I Corporation Features High-Density Programmable Logic Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 14000 PLD Gates — 480 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

IC 3160

Contextual Info: Lattice is p L S i Coiîporationît0r r 3 1 6 0 Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 7000 PLD Gates — 320 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Lattice' ispLSI 3320 | Semiconductor I Corporation Features High-Density Programmable Logic Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 160 I/O Pins — 14000 PLD Gates — 480 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

A3D instruction manual

Abstract: free home theater circuit diagram for assemble thx 203 ZR38000 spatializer zoran zr zoran dvd ZR38600 THx 206 Zoran 4100
Contextual Info: ZR38650 PROGRAMMABLE DIGITAL AUDIO PROCESSOR DATA SHEET FEATURES • Full-Function Digital Audio Processor Hardware - 50 MIPS performance with multi-operation instructions - Large internal RAMs/ROM plus low-cost external memory - Wide selection of on-chip digital audio peripherals

Contextual Info: LS211 ' * - I-Cube* 49 Port LAN Switching Element D escription Features • Single chip, Fast Ethernet switching fabric • Up to 100 M bit per-port switching capacity • Supports 49 full duplex ports • Four dedicated programmable output ports for M ulticast, port mirroring, or other port usage

SA11

Abstract: SC310 10-pin jtag diode in48 only112
Contextual Info: PRELIMINARY Élan SC310 TM Single-Chip, 32-Bit, PC/AT Microcontroller DISTINCTIVE CHARACTERISTICS Highly Integrated, Single-Chip CPU and System Logic — Optimized for embedded PC applications — Combines 32 bit, x86 compatible, low-voltage CPU with memory controller, PC/AT peripheral

Contextual Info: Lattice' ispLSr 3192 | Semiconductor I Corporation High Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

spo2 sensor

Abstract: AC73X "Capacitive Touch Sensor" spo2 algorithm SX9510 SX9510ETSTRT toshiba RC6 IR SpO2
Contextual Info: SX9510/11 8 Capacitive Buttons, LEDs, IR Decoder and Proximity Controller with Analog Outputs WIRELESS & SENSING PRODUCTS GENERAL DESCRIPTION The SX9510 and SX9511 are 8–button capacitive touch sensor controllers that include 8-channels of LED drivers, a buzzer, an IR detector and analog

IC 40106 pin diagram

Abstract: cmos ALL 4000- 4001- 4002 TO 4099 series IN MOTOROLA signetics hand book SDFD001B SN74368A cd4536 74HCT 4013 CD4000 SERIES BOOK SDLS051 40106 internal circuit diagram
Contextual Info: SN54ABT646A, SN74ABT646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUPUTS SCBS069G – JULY 1991 – REVISED MAY 1997 D D D D SN54ABT646A . . . JT OR W PACKAGE SN74ABT646A . . . DB, DW, NT, OR PW PACKAGE TOP VIEW CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7

Contextual Info: AMDÌ1 PRELIMINARY Élan SC300 Highly Integrated, Low-Power, 32-Bit Microcontroller DISTINCTIVE CHARACTERISTICS - Zero wait-state access with 70 ns, Page mode DRAMs • Highly integrated, single-chip CPU and system logic - Supports up to 16 Mbyte system memory

n20s

Abstract: CY3600 CY37512 CY37512V 0228l
Contextual Info: C Y37512 PR ELIMINA RY UltraLogic 512-Macrocell ISR™ CPLD — tc o = 6 ns Features • P ro d uct-term clocking • 512 m a cro c ells in 32 logic blo cks • IEEE 1149.1 JTAG b o u n d a ry scan • In-S ystem R ep ro g ra m m ab le ™ IS R ™ • P ro g ram m ab le slew rate control on ind ividu al l/O s

spw 068

Contextual Info: Accelerator Series FPGAs - ACT 3 Family F e a tu re s • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic

Contextual Info: P R E LIM IN A R Y AMDH Élan SC300 Highly Integrated, Low-Power, 32-Bit Microcontroller DISTINCTIVE CHARACTERISTICS — Zero wait-state access with 70 ns, Page mode DRAMs • Highly Integrated, Single-Chip CPU and System Logic — Optimized for handheld systems

ATIC 107

Contextual Info: ispGDX Family Lattica In-System Programmable Generic Digital Crosspoint I Sem iconductor I Corporation Features Functional Block Diagram IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CRO SSPOINT FAMILY ISP Control I/O Pins D — Advanced Architecture Addresses Programmable

A12L

Abstract: A13L IDT70V3569 IDT70V3569S "Dual-Port RAM"
Contextual Info: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode

H107L

Abstract: W32 MARKING MC 68 H 705 da 128 H217H L117l
Contextual Info: MIL-M-38510/202B 25 May 1984 s u P E R S tu n rc MIL-M-38510/202A 24 May 1982 QUALIFICATION REQUIREMENT REMOVED M ILIT A R Y S P EC IFIC A T IO N M IC RO CIRCU ITS. D IG IT A L , 1024 » IT » IM * . » « P*0eR»HH»BLE READ-ONL t MEMORY P-RO M , MONOLITHIC SILIC O N _

asx340

Abstract: je 243 PLK3210 109-149 IQX160 JE 33 IQX128B IQX240B IQX320 se 336
Contextual Info: Introduction T his m anual provides the inform ation needed to configure th e IQ X Fam ily devices using the JT A G interface. It is in ten d ed fo r u sers w ho p lan to w rite th eir ow n code to configure the IQ X devices. In addition, this m anual explains

FPQ-256

Abstract: TSC695 F User Manual transistor bra 94 TSC695 E310D bra15 FPQ-256-0 Flash SIMM 72 29F040 SPARC V7.0 ERC32
Contextual Info: eVAB-695 Rad-Hard Evaluation Board TSC695 Embedded Processor Hardware User’s Manual Rev.E - 22 March, 2001 1 eVAB-695 Hardware User’s Manual Information Foreword Atmel Nantes S.A. reserves the right to make changes in the products or specifications contained in this document