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    7 INPUTS OR GATE Search Results

    7 INPUTS OR GATE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TC4001BP Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, 2-Input/AND, DIP14 Visit Toshiba Electronic Devices & Storage Corporation
    74HC08D Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, 2-Input/AND, SOIC14 Visit Toshiba Electronic Devices & Storage Corporation
    TC4011BP Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, 2-Input/NAND, DIP14 Visit Toshiba Electronic Devices & Storage Corporation
    TC4093BP Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, 2-Input/NAND, DIP14 Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G32NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), 2-Input/OR, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation

    7 INPUTS OR GATE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    74LVC2G86

    Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT JESD22-A114E MO-187
    Text: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 05 — 7 September 2007 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		74LVC2G86 74LVC2G86 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT JESD22-A114E MO-187 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate Rev. 1 — 7 May 2013 Product data sheet 1. General description The 74LVC2G86-Q100 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		74LVC2G86-Q100 74LVC2G86-Q100 74LVC2G86 PDF

    HI-8482

    Abstract: No abstract text available
    Text: HI-8482 ARINC 429 DUAL LINE RECEIVER The self-test inputs force the outputs to either a ZERO, ONE, or NULL state for system tests. While in self-test mode, the ARINC inputs are ignored. IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8 All the ARINC inputs have built-in hysteresis to reject


    Original     		HI-8482 HI-8482 RM3183. 20-PIN PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G86 74AUP2G86 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		74AUP2G86 74AUP2G86 PDF

    C8051F360

    Abstract: Silabs CIP-51 TQFP-48 79ma f36012 CPS20
    Text: C8051F360/1/2/3/4/5/6/7/8/9 Mixed Signal ISP Flash MCU Family Analog Peripherals - 10-Bit ADC ‘F360/1/2/6/7/8/9 only • Up to 200 ksps • Up to 21 external single-ended or differential inputs • VREF from internal VREF, external pin or VDD • Internal or external start of conversion source


    Original     		C8051F360/1/2/3/4/5/6/7/8/9 10-Bit F360/1/2/6/7/8/9 F360/1/2/3/4/5/6/7) F368/9) C8051F360 Silabs CIP-51 TQFP-48 79ma f36012 CPS20 PDF

    HA132

    Abstract: A115-A C101 SN54AHC132 SN74AHC132
    Text: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC


    Original     		SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 HA132 A115-A C101 SN54AHC132 SN74AHC132 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC


    Original     		SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 PDF

    SCLS365

    Abstract: A115-A C101 SN54AHC132 SN74AHC132
    Text: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC


    Original     		SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 SCLS365 A115-A C101 SN54AHC132 SN74AHC132 PDF

    ha132

    Abstract: A115-A C101 SN54AHC132 SN74AHC132
    Text: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC


    Original     		SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 ha132 A115-A C101 SN54AHC132 SN74AHC132 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC


    Original     		SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC


    Original     		SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 PDF

    74LCX32

    Abstract: No abstract text available
    Text: s=7 SGS-THOMSON Ä 7# KfflO g«LiM (s iO (gS 74LC X32 LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE 5V TOLERANT INPUTS AND OUTPUTS PRELIMINARY DATA . 5VTOLERAr\TT INPUTS . HIGHSPEED: tpD = 5.5 ns (MAX.) at VCc = 3V . POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS . SYMMETRICAL OUTPUT IMPEDANCE:


    OCR Scan     		74LCX32M 74LCX32T 500mA LCX32 74LCX32 PDF

    74LCX86

    Abstract: No abstract text available
    Text: s = 7 ^ 7 # S G S -T H O M S O N K l g K L iM ( s iO ( g S 74LCX86 LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE WITH 5V TOLERANT INPUTS PRELIMINARY DATA . 5VTOLERAr\TT INPUTS . HIGHSPEED: tpD = 6.5 ns (MAX.) at VCc = 3V . POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS


    OCR Scan     		74LCX86 74LCX86M 74LCX86T 74LCX86 PDF

    LCX32

    Abstract: 74LCX32
    Text: rZ T Ä 7# S G S -T H O M S O N 74LC X32 LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE 5V TOLERANT INPUTS AND OUTPUTS PRELIMINARY DATA . 5V TOLERANT INPUTS . HIGHSPEED: tpD = 5.5 ns MAX. at Vcc = 3V . POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS . SYMMETRICAL OUTPUT IMPEDANCE:


    OCR Scan     		74LCX32M 74LCX32T p10MHz 74LCX32 LCX32 74LCX32 PDF

    54164

    Abstract: No abstract text available
    Text: SN54164, SN54LS164. SN74164, SN74LS164 8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS M ARCH 1974 - REVISED M AR CH 1988 • Gated Serial Inputs SN 54164, SN 54LS164 . . . J OR W PACKAG E SN 74164 . . . N PACKAG E S N 7 4 L S 1 6 4 . . . D OR N P A C K A G E • Fully Buffered Clock and Serial Inputs


    OCR Scan     		SN54164, SN54LS164. SN74164, SN74LS164 54LS164 LS164 54164 PDF

    54164

    Abstract: IC 74164
    Text: SN54164, SN 54LS164, SN74164, S N 74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS MAR C H 1 9 7 4 - REVISED M AR C H 1988 Gated Serial Inputs S N 5 4 1 6 4 , S N 54 L S 1 6 4 . . . J OR W PACKAGE • Fully Buffered Clock and Serial Inputs S N 7 4 1 6 4 . . . N PACKAGE


    OCR Scan     		SN54164, 54LS164, SN74164, 74LS164 54164 IC 74164 PDF

    54HC165

    Abstract: 4HC165
    Text: SN54HC165, SN74HC165 PARALLEL LOAD 8-BIT SHIFT REGISTERS D2684. DECEMBER 1982-REVISED SEPTEMBER 1987 Complementary Outputs S N 5 4 H C 1 6 5 . . . J PACKAGE S N 7 4 H C 1 6 5 . . . D OR N PACKAGE Direct Overriding Load Data Inputs (TOP VIEW } Gated Clock Inputs


    OCR Scan     		SN54HC165, SN74HC165 D2684. 1982-REVISED 300-m gis150 SN74H 54HC165 4HC165 PDF

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA INFORMATION TC74VCX32FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 7 4 V C X 3 2 FT LOW-VOLTAGE QUAD 2-INPUT OR GATE WITH 3.6V TOLERANT INPUTS AND OUTPUTS The TC74VCX32FT is a high performance CMOS 2-INPUT OR GATE. Designed for use in 1.8, 2.5 or 3.3 Volt


    OCR Scan     		TC74VCX32FT TC74VCX32FT TSSOP14-P-0044-0 55TYP PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11881,74ACT11881 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS D3480, MARCH 1990 54ACT11881 . . . JT OR JW PACKAGE 74ACT11881 . . . DW OR NT PACKAGE Inputs are TTL-Voltage Compatible Full Look-Ahead for High-Speed Operations on Long Words TOP VIEW T 7


    OCR Scan     		54ACT11881 74ACT11881 D3480, 54ACT11881 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008C - JULY 1 9 8 7 - REVISED APRIL 1996 Inputs Are TTL-Voltage Compatible D, DB, N, OR PW PACKAGE TOP VIEW Center-Pin Vcc and GND Configurations to Minimize High-Speed Switching Noise 1A[ 1 1Y [ 2 2Y[ 3


    OCR Scan     		74ACT11032 SCAS008C 500-mA 300-mil perf03 010S4L0 PDF

    74hc4075

    Abstract: No abstract text available
    Text: T -4.vai-O D Technical Data — CD54/74HC4075 CD54/74HCT4075 File Number 1 7 7 8 HARRIS SEMICOND SECTOR 27E D M302571 0017^55 A BiHAS High-Speed CMOS Logic Triple 3-Input OR Gate Type Features: • Buffered inputs ■ Typical CD54/74HC4075 Propagation Delay = 8ns


    OCR Scan     		CD54/74HC4075 CD54/74HCT4075 M302571 RCA-CD54/74HC4075 CD54/74HCT4075 CD54/74HCT 54LS/74LS CDS4HC4075 CD54HCT40- 74hc4075 PDF

    hd74ls138 data

    Abstract: ic yo 1S2074 74LSOO HD74LS138
    Text: HD74LS138 3-Une-to-8-Line Decoders/Demultiplexers The H D 7 4 L S1 3 8 decodes one-of-eight line dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable in­ puts reduce the need for external gates or inverters when


    OCR Scan     		HD74LS138 24-line 32-line QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 hd74ls138 data ic yo 1S2074 74LSOO PDF

    IC ATA 2388

    Abstract: ATA 2388 hct373a C74HCTXXXADT
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA O ctal 3 -S ta te Noninverting Transparent Latch w ith LSTTL-C om patible Inputs High-Performance Silicon-Gate CMOS The M C 5 4 /7 4 H C T 3 7 3 A m ay be u se d as a le v e l c o n v e rte r fo r interfacing TTL or NMOS outputs to H igh-S peed CMOS inputs.


    OCR Scan     		HCT373A LS373. IC ATA 2388 ATA 2388 C74HCTXXXADT PDF