64MACRO Search Results

Contextual Info: FINAL IND: -10/12/14/18/24 COM’L: -7.5/10/12/15/20 a Advanced Micro Devices M A C H 2 1 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 64Macrocells ■ Programmable power-down mode ■ 7.5 ns î p d Commercial

4032V

Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

vp44

Abstract: CY37064 CY37064V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY CY37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks

Contextual Info: EPM5064 EPLD Features • ■ ■ ■ ■ ■ ■ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tpu as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 128 shareable expander product terms "expanders" allowing over

Ultra37064

Abstract: CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress
Contextual Info: J ^ m n rn n : if : Y PRELIMINARY H Ultra37064 - UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tc o = 4.5 ns • 64 m a cro cells in fo u r logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

MX 0541

Abstract: mx 0541 b CY7C373
Contextual Info: fax id: 6138 CY7C373Ì CYPRESS UltraLogic 64-Macrocell Flash CPLD Functional Description Features • 64 m a cro cells in fo u r logic blocks The C Y 7 C 3 73i is an In-System R eprogram m able C om plex P rogram m able Logic Device CPLD and is pa rt of the

CY7C373

Abstract: CY7C374 FLASH370
Contextual Info: For new designs see CY7C373i CY7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks The CY7C373 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the FLASH370TM family of

c3431

Abstract: C3438 c3432 CY7C343 c3435 C343-8
Contextual Info: CY7C343 64-Macrocell MAX EPLD Features • • • • • • The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that

4064ZE

Abstract: 4000ZE 64-marocells
Contextual Info: ispMACH 4000ZE - Enabling CPLDs in Ultra High Volume, Low Power Applications A Lattice Semiconductor White Paper April 2008 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: 503 268-8000 www.latticesemi.com 1 ispMACH 4000ZE - Enabling CPLDs in Ultra High Volume, Low Power Applications

IPTV STB

Abstract: AN8080 4000ZE TN1187
Contextual Info: THE IMPACT OF ENERGY EFFICIENCY STANDARDS ON STANDBY POWER IN CONSUMER ELECTRONICS DESIGN A Lattice Semiconductor White Paper May 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: 503 268-8000 www.latticesemi.com

Contextual Info: fax id: 6137 CY7C372Ì ^CYPRESS UltraLogic 64-Macrocell Flash CPLD Features • • • • F LA SH 370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the C Y 7 C 3 7 2 i is de­ signed to bring the ease of use and high performance of the

Contextual Info: W CYPRESS CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Functional Description Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: CY7C372 PRELIMINARY CYPRESS SEMICONDUCTOR 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed The CY7C372 is a Flash Erasable Pro­

Contextual Info: fax id: 6128 CYPRESS CY7C373 UltraLogic 64-Macrocell Flash CPLD FLASH370 fam ily the CY7C373 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Features • 64 macrocells in four logic blocks • 64 I/O pins The 64 macrocells in the CY7C373 are divided between four

qfg48 dimensions

Abstract: XC2C64A-7CPG56I XC2C64A-7QFG48I XC2C64A-7VQG100C XC2C64A-7VQG44C LVCMOS33 XAPP427 XC2C64A DS092 LVCMOS25
Contextual Info: R DS311 v1.3 November 8, 2004 XC2C64A CoolRunner-II CPLD Advance Product Specification Features Description • The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and

smd transistor w16

Abstract: transistor smd w16 PALC22V10B-15DMB 256K x 8 SRAM CY7C128A SRAM PALC22V10B-20DMB Mil JAN jm38510 Cross Reference smd cross reference smd w20 CY7C245-45WMB 455b
Contextual Info: SMD Cross Reference Listed below are the SMDs for which Cypress is an approved source of supply. Please contact your local Cypress representative or see the Cypress website www.cypress.com for the latest SMD update. All part numbers that have an X in the PPL (Preferred

allocator

Contextual Info: CY7C373Ì PRELIMINARY UltraLogic 64-Macrocell Flash CPLD Features Device CPLD and is part of the FLASH370i™ family of high-density, high­ speed CPLDs. Like all members of the F lash 37(H family, the CY7C373i is de­ signed to bring the ease of use and high

CY37064

Contextual Info: UltraLogic 64-Macrocell ISR™ CPLD — ts = 3.5 ns Features — tCo = 4 -5 ns • Product-term clocking 64 macrocells in four logic blocks In-System Reprogrammable™ ISR™ • IEEE 1149.1 JTAG boundary scan • Programmable slew rate control on individual l/Os

transistor c343

Abstract: c343 diode lattice im4a3 CY7C343
Contextual Info: CY7C343 64-Macrocell MAX EPLD Features • • • • • • The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that

DS092

Abstract: LVCMOS15 LVCMOS25 LVCMOS33 XAPP427 XC2C64 XC2C64A VQ1001 5VQ10 G1142
Contextual Info: R DS092 v2.1 March 7, 2005 XC2C64 CoolRunner-II CPLD Note: This product is no longer recommended for new designs. It has been superseded by the XC2C64A, a device with I/O Banking and Pb-free package options. • • • Refer to the CoolRunner -II family data sheet for architecture description.

Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs November 2013 Data Sheet DS1020  Broad Device Offering Features • Multiple temperature range support – Commercial: 0 to 90°C junction Tj – Industrial: -40 to 105°C junction (Tj)

EPM3256ATC144-7

Abstract: verilog hdl code for 4 to 1 multiplexer in quartus 2 EPM3064ATC100-4 EPM3256A EPM3064A verilog code for switch Crosspoint Switches AN-294
Contextual Info: Crosspoint Switch Matrices in MAX 3000A Devices February 2003, ver. 1.0 Introduction Application Note 294 With a high level of flexibility, performance, and programmability, you can use crosspoint switches in applications such as digital cross switching, telecommunications, and video broadcasting. Although there are off-theshelf devices available to implement switches, Altera MAX® devices offer

lem lta 100p

Abstract: lem la 100-P CY37064
Contextual Info: CY37064 PR EU M IN Am UltraLogic 64-Macrocell ISR™ CPLD — ts = 4.0 ns Features — t co = 4.0 ns • 64 m a cro c ells in fo u r log ic blocks P ro d uct-term clo ckin g • In-S ystem R e p ro g ra m m ab le ™ IS R ™ JT A G -co m p liant o n-b oard p ro gram m in g

Contextual Info: fax id: 6137 CY7C372Î C'i- UltraLogic 64-Macrocell Flash CPLD Features FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the Fi_ASH370i family, the CY7C372i is de­ signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to