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    54LS11 Search Results

    54LS11 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    54LS113A/BCA Rochester Electronics LLC 54LS113A - FLIP-FLOP, JK, DUAL, WITH PRESET AND CLEAR - Dual marked (M38510/30104BCA) Visit Rochester Electronics LLC Buy
    54LS113FM/B Rochester Electronics LLC 54LS113 - Dual JK Neg-Edge-Triggered FF w/preset Visit Rochester Electronics LLC Buy
    SNJ54LS11W Texas Instruments Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 Visit Texas Instruments Buy
    SNJ54LS11J Texas Instruments Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 Visit Texas Instruments Buy
    SNJ54LS112AJ Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 Visit Texas Instruments Buy
    SF Impression Pixel

    54LS11 Price and Stock

    Rochester Electronics LLC 54LS112FM

    J-K FLIP-FLOP
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    DigiKey 54LS112FM Bulk 202
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    Rochester Electronics LLC SNJ54LS11J

    IC TRPL 3-INP
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    DigiKey SNJ54LS11J Bulk 30
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    Rochester Electronics LLC SN54LS112AJ

    J-K FLIP-FLOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN54LS112AJ Bulk 30
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    Rochester Electronics LLC 54LS113FM-B

    DUAL JK NEG-EDGE-TRIGGERED FF W/
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    DigiKey 54LS113FM-B Bulk 4
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    Rochester Electronics LLC DM54LS11J-883

    IC GATE AND 3CH 3-INP 14CERDIP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey DM54LS11J-883 Bulk 139
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    Find more 54LS11 price and stock on Findchips.com

    54LS11 Datasheets (78)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS11 National Semiconductor Triple 3-Input AND Gates Original PDF
    54LS11 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS11 Unknown TRIPLE 3-INPUT AND GATE Scan PDF
    54LS11 Raytheon Positive-AND Gates Scan PDF
    54LS112 National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OP Original PDF
    54LS112 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS112 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
    54LS112A/BEAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112A/BFAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112DM Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    54LS112DM Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112DMQB Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112DMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112DMQB National Semiconductor DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET CLEAR and COMPLEMENTARY OUTPUTS Scan PDF
    54LS112DMQB National Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112FM Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    54LS112FMQB Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs Scan PDF
    54LS112FMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS112FMQB National Semiconductor DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET CLEAR and COMPLEMENTARY OUTPUTS Scan PDF

    54LS11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 54LS11,54LS11,DM74LS11 54LS11 54LS11 DM74LS11 Triple 3-Input AND Gates Literature Number: SNOS279A 54LS11 54LS11 DM74LS11 Triple 3-Input AND Gates General Description Features This device contains three independent gates each of which performs the logic AND function


    Original     		PDF 54LS11 DM54LS11 DM74LS11 DM74LS11 SNOS279A

    dm74ls112an

    Abstract: 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112A DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM
    Text: 54LS112 54LS112A DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and


    Original     		PDF 54LS112 DM54LS112A DM74LS112A dm74ls112an 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM

    54LS113

    Abstract: 54LS 54LS113DMQB 54LS113FMQB 54LS113LMQB C1995 E20A J14A W14B
    Text: 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the bistable


    Original     		PDF 54LS113 54LS113 54LS113DMQB 54LS113FMQB 54LS113LMQB 54LS 54LS113DMQB 54LS113LMQB C1995 E20A J14A W14B

    Untitled

    Abstract: No abstract text available
    Text: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE


    OCR Scan     		PDF 54LS112A 74LS112A

    Untitled

    Abstract: No abstract text available
    Text: TYPES SN54H11, 54LS11, SN54S11, SN74H11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES R E V IS E D A P R IL 1 S 8 5 Dependable Texas Instruments Quality and Reliability SN54H11 . . . J PACKAGE SN 54LS11, SN 54 S1 1 . . . J OR W PACKAGE SN 74H11 . . . J OR N PACKAGE


    OCR Scan     		PDF SN54H11, SN54LS11, SN54S11, SN74H11, SN74LS11, SN74S11 SN54H11 54LS11, 74H11 74LS11,

    dm74 Series

    Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
    Text: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS112/DM54LS112A/DM74LS112A dm74 Series 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM

    54LS113

    Abstract: No abstract text available
    Text: LS113 H t] National Juâ Semiconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may


    OCR Scan     		PDF LS113 54LS113

    Untitled

    Abstract: No abstract text available
    Text: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the


    OCR Scan     		PDF LS112A 54LS112/DM54LS112A/DM74LS112A

    CP12A-1

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 54LS112A D u a l J -K Flip-Flop W ith C le a r an d Pre se t ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asyn­ chronous set and clear inputs to each flip-flop. When the clock goes


    OCR Scan     		PDF MIL-M-38510/30103 54LS112A 54LS112A JM38510/30103BXA 54LS112A/BXAJC CP12A-1

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O L A Military 54LS114A D u a l J -K Flip-Flop W ith Preset, C o m m o n C le ar and C o m m o n C lo c k MIL-M-38510/30105 T h e 5 4 L S 1 1 4 A o ffe rs c o m m o n clock a n d c o m m o n clear inputs and in d ivid u al J, K, and set inputs. Th e se m o n o lith ic dual flip -flo p s are


    OCR Scan     		PDF MIL-M-38510/30105

    Untitled

    Abstract: No abstract text available
    Text: M ilita ry 5 4 L S 1 1 <8> M O T O R O L A Triple 3-Input P ositive AND G ate MP0 m ini ELECTRICALLY TESTED PER: MIL-M-38510/31001 LOGIC DIAGRAM Vcc C1 Y1 C3 B3 A3 Y3 AVAILABLE AS: 1 JAN: JM38510/31001BXA 2) SMD: N/A 3)883: 54LS11/BXAJC X = CASE OUTLINE AS FOLLOWS:


    OCR Scan     		PDF MIL-M-38510/31001 JM38510/31001BXA 54LS11/BXAJC 56A-02

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic A N D function. Features • Alternate m ilitary/aerospace device 54LS11 is available. C ontact a Fairchild Sem iconductor Sales


    OCR Scan     		PDF DM74LS11 54LS11) DSOO6350-1 54LS11DMQB, 54LS11FMQB, 54LS11LMQB, DM54LS11J, DM54LS11W, DM74LS11M

    74LS11

    Abstract: 74S11 54ls11
    Text: S N 54LS11, SN54S11, SN 74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE AND GATES A PRIL 19 85 —R EV ISED MARCH 1988 S N 5 4 L S 1 1 . S N 7 4 S 1 1 . . . J OR W P A C K A G E SN 74LS11. SN 74S11 c 1 U 14 : 13 : 2 12 q 3 11 : c4 10 c 5 9 : c6 1A c IB Dependable Texas Instruments Quality and


    OCR Scan     		PDF 54LS11, SN54S11, 74LS11, SN74S11 74LS11 74LS11. 74S11 54ls11

    Untitled

    Abstract: No abstract text available
    Text: 8 < > M ilitary 54LS114A MOTOROLA Dual J -K Flip-Flop W ith P reset, Common C lear and Com m on C lock MPO MIL-M-38510/30105 unw The 54LS114A offers common clock and common clear inputs and individual J, K, and set Inputs. These monolithic dual flip-flops are


    OCR Scan     		PDF 54LS114A MIL-M-38510/30105 54LS114A JM38510/30105BXA 54LS114A/BXA=

    pr 5104

    Abstract: UTRX
    Text: ^ M O T O R O L A M ilitary 54LS 113A Dual J-K Flip-Flop W ith P reset MPO lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH,


    OCR Scan     		PDF MIL-M-38510/30104 54LS113A JM38510/30104BXA 54LS113A/BXAJC pr 5104 UTRX

    LS114

    Abstract: No abstract text available
    Text: ^ National Semiconductor 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’L S 1 14 features individual J, K and set inputs and com­ mon clock and common clear inputs. When the clock goes HIGH the inputs are enabled and data will be accepted. The


    OCR Scan     		PDF 54LS114 LS114 LS114

    54ls11

    Abstract: No abstract text available
    Text: June 1989 54LS11/54LS11/DM74LS11 Triple 3-Input AND Gates General Description Features This device contains three independent gates each of which performs the logic AND function. • Alternate military/aerospace device 54LS11 is available. Contact a National Semiconductor Sales Office/


    OCR Scan     		PDF 54LS11/DM54LS11/DM74LS11 54LS11) 54LS11DMQB, 54LS11FMQB, 54LS11LMQB, DM54LS11J, DM54LS11W, DM74LS11M DM74LS11N 54ls11

    Untitled

    Abstract: No abstract text available
    Text: & June 1989 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and


    OCR Scan     		PDF 54LS112/DM54LS112A/DM74LS112A

    SN54LS114A

    Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
    Text: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation


    OCR Scan     		PDF SN54LS114A, SN54S114, SN74LS114A, SN74S114A SN54S114. SN54LS114A SN54S114 SN74 SN74LS114A LS114

    Untitled

    Abstract: No abstract text available
    Text: LS11 01 National itiI Semiconductor 54LS11/54LS11/DM74LS11 Triple 3-Input AND Gates General Description Features This device contains three independent gates each of which performs the logic AND function. • Alternate military/aerospace device 54LS11 is avail­


    OCR Scan     		PDF 54LS11/DM54LS11/DM74LS11 54LS11) 54LS11DMQB, 54LS11FMQB, 54LS11LMQB, DM54LS11J, DM54LS11W, DM74LS11M DM74LS11N

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O M ilitary 54LS114A L A Dual J -K Flip-Flop W ith P reset, Com m on C lear and Com m on C lock M MIL-M-38510/30105 P O H U M The 54LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are


    OCR Scan     		PDF 54LS114A MIL-M-38510/30105 54LS114A JM38510/30105BXA

    Untitled

    Abstract: No abstract text available
    Text: LS113 National J j I Semiconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may


    OCR Scan     		PDF 54LS113 54LS113DMQB, 54LS113FMQB 54LS113LMQB TL/F/10205-1 TL/F/10205â

    Untitled

    Abstract: No abstract text available
    Text: S E M IC O N D U C T O R tm DM74LS11 Triple 3-Input AND Gates General Description This device contains three independent gates each of which perform s the logic AN D function. Features • Alternate m ilitary/aerospace device 54LS11 is available. C ontact a Fairchild Sem iconductor Sales


    OCR Scan     		PDF DM74LS11 54LS11) DS006S50-1 54LS11DMQB, 54LS11FMQB, 54LS11LMQB, DM54LS11J, DM54LS11W, DM74LS11M

    Untitled

    Abstract: No abstract text available
    Text: M O TO R O LA Military 54LS11 Triple 3-Input Positive AND Gate ELECTRICALLY TESTED PER: MIL-M-38510/31001 LOGIC DIAGRAM V cc ci VI C3 B3 AVAILABLE AS . A3 « 1 JA N : JM 38510/31001BXA 2) SM D: * 3) 883C: 54LS11/BXAJC i*r r 41 X = CASE O UTUNE AS FOLLOWS:


    OCR Scan     		PDF MIL-M-38510/31001 54LS11 38510/31001BXA 54LS11/BXAJC