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    54LS113 Search Results

    54LS113 Result Highlights (2)

    Part ECAD Model Manufacturer Description Download Buy
    54LS113FM/B Rochester Electronics LLC 54LS113 - Dual JK Neg-Edge-Triggered FF w/preset Visit Rochester Electronics LLC Buy
    54LS113A/BCA Rochester Electronics LLC 54LS113A - FLIP-FLOP, JK, DUAL, WITH PRESET AND CLEAR - Dual marked (M38510/30104BCA) Visit Rochester Electronics LLC Buy
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    54LS113 Price and Stock

    Rochester Electronics LLC 54LS113FM-B

    DUAL JK NEG-EDGE-TRIGGERED FF W/
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    DigiKey 54LS113FM-B Bulk 4
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    Rochester Electronics LLC DM54LS113W-883

    J-K FLIP-FLOP
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    DigiKey DM54LS113W-883 Bulk 31
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    Teledyne e2v 54LS113/B2A

    FLIP-FLOP, JK, DUAL, WITH PRESET AND CLE - Rail/Tube (Alt: 54LS113/B2A)
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    Teledyne e2v 54LS113/BXA

    FLIP-FLOP, JK, DUAL, WITH PRESET AND CLE - Rail/Tube (Alt: 54LS113/BXA)
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    Teledyne e2v 54LS113/BCA

    FLIP-FLOP, JK, DUAL, WITH PRESET AND CLE - Rail/Tube (Alt: 54LS113/BCA)
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    Find more 54LS113 price and stock on Findchips.com

    54LS113 Datasheets (14)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54LS113 National Semiconductor Dual JK Edge Triggered Flip-Flop Original PDF
    54LS113 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    54LS113 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
    54LS113A/BCAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113A/BDAJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113AM/B2AJC Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113DM Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    54LS113DMQB National Semiconductor Dual JK Edge-Triggered Flip-Flop Original PDF
    54LS113DMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113FM Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    54LS113FMQB National Semiconductor Dual JK Edge-Triggered Flip-Flop Original PDF
    54LS113FMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    54LS113LMQB National Semiconductor Dual JK Edge-Triggered Flip-Flop Original PDF
    54LS113LMQB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    54LS113 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    54LS113

    Abstract: 54LS 54LS113DMQB 54LS113FMQB 54LS113LMQB C1995 E20A J14A W14B
    Text: 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the bistable


    Original     		PDF 54LS113 54LS113 54LS113DMQB 54LS113FMQB 54LS113LMQB 54LS 54LS113DMQB 54LS113LMQB C1995 E20A J14A W14B

    ay-5-1012

    Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
    Text: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS


    Original     		PDF 38510/MACH Mll-M-38510 Z501300 Z501200 Z501201 Z012510 ZOl1510 ay-5-1012 ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor

    m38510/06301

    Abstract: M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302
    Text: JAN/SMD Devices JAN/SMD Source JAN/SMD Source JAN/SMD Source M38510/00101 5430 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 5420 M38510/07702 54S139 M38510/31601 54LS75 M38510/00103 5410 M38510/07801 54S181 M38510/31603 54LS259 M38510/00104 5400


    Original     		PDF M38510/00101 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 M38510/07702 54S139 M38510/31601 54LS75 m38510/06301 M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302

    54LS113

    Abstract: No abstract text available
    Text: LS113 H t] National Juâ Semiconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may


    OCR Scan     		PDF LS113 54LS113

    pr 5104

    Abstract: UTRX
    Text: ^ M O T O R O L A M ilitary 54LS 113A Dual J-K Flip-Flop W ith P reset MPO lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH,


    OCR Scan     		PDF MIL-M-38510/30104 54LS113A JM38510/30104BXA 54LS113A/BXAJC pr 5104 UTRX

    Untitled

    Abstract: No abstract text available
    Text: LS113 National J j I Semiconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may


    OCR Scan     		PDF 54LS113 54LS113DMQB, 54LS113FMQB 54LS113LMQB TL/F/10205-1 TL/F/10205â

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O L A Military 54LS113A Dual J-K Flip-Flop With Preset M ELECTRICALLY TESTED PER: MIL-M-38510/30104 P O m in i T h e 5 4 L S 1 1 3 A o ffe r s in d iv id u a l J , K , s e t, a n d c lo c k in p u ts . T h e s e m o n o lith ic d u a l flip -flo p s a r e d e s ig n e d s o th a t w h e n th e c lo c k g o e s H I G H ,


    OCR Scan     		PDF 54LS113A MIL-M-38510/30104 JM38510/30104BXA 54LS113A/BXAJC

    motorola ic 6116

    Abstract: No abstract text available
    Text: M m o to r o la Military 54LS113A D u a l J -K Flip -Flo p W ith P re se t ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A o ffe rs in d ivid u a l J, K, set, and clock in p u ts. These m o n o lith ic dual flip -flo p s are designed so th a t w hen th e clock goes


    OCR Scan     		PDF 54LS113A MIL-M-38510/30104 54LS113A JM38510/30104BXA 54LS1F, motorola ic 6116

    SN54S113

    Abstract: SN74LS113A SN54LS113A SN74 SN74S113A
    Text: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISED MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS113A . S N 54S 113 . . . J OR W PACKAGE SN 74LS 113A . S N 74S 113A . . . O OR N PACKAGE


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113A D2661, SN54S113 SN74LS113A SN54LS113A SN74

    Untitled

    Abstract: No abstract text available
    Text: LS113 CT1 National 4 j t Sem iconductor 54LS113 Dual JK Edge-Triggered Flip-Flop General Description The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may


    OCR Scan     		PDF LS113 54LS113 54LS113

    S113

    Abstract: SN54LS113A SN54S113 SN74 SN74LS113A SN74S112 SN74S113
    Text: TYPES 54LS113A, SN54S113, SN74LS113A, SN74S113 DUAL J -K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET REVISED DECEMBER 1983 F u lly B u ffe re d to O ffe r M a x im u m Isola tio n fro m E xtern al D is tu rb a n c e S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W PACKAG E


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113 S113 SN54LS113A SN54S113 SN74 SN74LS113A SN74S112

    74s188 programming

    Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
    Text: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE


    OCR Scan     		PDF 38510/MACH MIL-M-38510 74s188 programming 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 5 4 LS 7 3 A Dual J-K Flip-Flop With Clear ELECTRICALLY TESTED PER: MIL-M-38510/30101 The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that w hen the clock goes HIGH, the inputs are enabled and data will be accepted. The logic of the J and K inputs may


    OCR Scan     		PDF MIL-M-38510/30101 54LS73A JM38510/30101BXA 54LS73A/BXAJC 54LS113A

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


    OCR Scan     		PDF

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		PDF 54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


    OCR Scan     		PDF

    54LS641

    Abstract: CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623
    Text: MAXIMUM RATINGS Supply Voltage - Vcc T h e S e rie s 5 4 L S /7 4 L S Schottky TTL family features both Schottky-barrier-diode inputs and em itte r inputs and u tilizes full Schottky-barrier-diode clamping to achieve speeds com parable to Series 54/74 at one-fifth of the


    OCR Scan     		PDF 54LS00 74LS00 24-LEAD 20-LEAD 54LS390/E 54LS393/C 54LS395A/E 54LS445/E 54LS490/E 54LS533/R 54LS641 CD Octal D-type flip-flop 74LS00 QUAD 2-INPUT NAND GATE 54LS642 54LS154 74LS00 quad TTL nand gate 74ls00 NAND gate SchottkyBarrierDiode 54LS92 54LS623

    74s113a

    Abstract: SN74LS113 74ls113a
    Text: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISEO MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W P A C K A G E


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113A D2661, 74s113a SN74LS113 74ls113a

    LG color tv Circuit Diagram schematics

    Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
    Text: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS


    OCR Scan     		PDF MIL-M-38510 38510/MACH 3186J Z501201 Z012510 Z011510 D022110 D022130 D021110 D021130 LG color tv Circuit Diagram schematics texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		PDF 24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilita ry 54L S 73A Dual J-K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30101 M mini The 5 4 L S 7 3 A offers individual J, K, clear, and clock inputs. These dual flip -flo p s are desig n ed so th a t w hen the clo ck g oe s HIG H , th e inputs


    OCR Scan     		PDF MIL-M-38510/30101 JM38510/30101BXA 54LS73A/BXAJC

    Untitled

    Abstract: No abstract text available
    Text: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISED MARCH 1988 Fully Buffered to Offer Meximum Isolation from External Disturbance SNS4LS113A. SN54S113 . . . J OR W PACKAGE SN74LS113A. SN74S113A . . . O OR N PACKAGE


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113A D2661, SNS4LS113A. SN54S113 SN74LS113A. 54LS1

    2650B

    Abstract: wf vqc 10d alu 9308 d Signetics 2650 SN52723 2650 cpu 82S103 pipbug Signetics NE561 cd 75232
    Text: flcnCTICf ßii>ouiR/mos fflICROPROCEÍSOR DATfl mnnuni SIGNETICS reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the


    OCR Scan     		PDF

    SN74LS113A

    Abstract: No abstract text available
    Text: TYPES 54LS113A, SN54S113, SN74LS113A, SN74S113 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET REVISED DECEMBER 1983 Fully Buffered to O ifer M axim um Isolation fro m External Disturbance S N 54LS 113A , S N 54S 113 . . . J OR W PACKAGE S N 74LS 113A , S N 74S 113 . . D , J OR N PACKAGE


    OCR Scan     		PDF SN54LS113A, SN54S113, SN74LS113A, SN74S113 SN74LS113A