54ACT11109 Search Results

Contextual Info: 54ACT11109, 74ACT11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET ăą SCAS451 − FEBRUARY 1987 − REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J

54ACT11109

Abstract: 74ACT11109 D2957 611H
Contextual Info: _ 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 0 6 7 — D 2 9 5 7 , F E B R U A R Y 1 9 8 7 — R E V I S E D J A N U A R Y 1 9 9 0 Inputs are TTL-Voltage Compatible 54ACT11109 . . . J P A C K A G E 74ACT11109 . . D O R N P A C K A G E

54ACT11109

Abstract: 74ACT11109
Contextual Info: 54ACT11109, 74ACT11109 DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET ăą SCAS451 − FEBRUARY 1987 − REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J

Contextual Info: 54ACT11109,74ACT11109 DUALJ-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, FEBRUARY 1987 - REVISED APRIL 1993_ logic symbol* 1Q 1Q 2Q 2Q t This symbol is In accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

54ACT11109

Abstract: 74ACT11109
Contextual Info: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K 54ACT11109 . . . FK PACKAGE

Contextual Info: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K 54ACT11109 . . . FK PACKAGE

Contextual Info: 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0067— D2957, FEBRUARY 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54AC T11109 . . . J PAC KAG E 74A C T11109 . . . D OR N PAC KAG E • Flow-Through Architecture to Optimize PCB

Contextual Info: 54ACT11109,74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ D29S7, FEBRUARY 1987 - REVISED APRIL 1993 54ACT11109. . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

54ACT109

Abstract: 54ACT11109 5962-8853401FX
Contextual Info: p . o REVISIONS LTR DATE YR-MO-DA DESCRIPTION APPROVED REV SHEET REV SHEET REV STATUS OF SHEETS RE•V I SHEET 2 3 PM ICN/A PREPARED BY STANDARDIZED MILITARY DRAWING CHECKEÍ-BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE

TSMC 0.18 um MOSfet

Abstract: M38510 10102BCA IDT7204L 5962-8768401MQA 0.18um LDMOS TSMC sl1053 TSMC 0.25Um LDMOS UT63M125BB SMD RTAX250S-CQ208 5962-04221
Contextual Info: DSCC Supplemental Information Sheet for Electronic QML-38535 Specification Details: Date: 9/2/2008 Specification: MIL-PRF-38535 Title: Advanced Microcircuits Federal Supply Class FSC : 5962 Conventional: No Specification contains quality assurance program: Yes

5962L0053605VYC

Abstract: 5962-9069204QXA ATMEL 302 24C16 UT9Q512E-20YCC MOH0268D UT54ACS164245SEIUCCR Z085810 5962-9762101Q2A UT28F256QLET-45UCC 5962R0250401KXA
Contextual Info: NOT MEASUREMENT SENSITIVE MIL-HDBK-103AJ 19 SEPTEMBER 2011 SUPERSEDING MIL-HDBK-103AH 28 MARCH 2011 DEPARTMENT OF DEFENSE HANDBOOK LIST OF STANDARD MICROCIRCUIT DRAWINGS This handbook is for guidance only. Do not cite this document as a requirement. AMSC N/A