Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    54ACT11020 Search Results

    SF Impression Pixel

    54ACT11020 Price and Stock

    Texas Instruments 54ACT11020FK

    NAND GATE; Temperature Grade: MILITARY; Terminal Form: NO LEAD; No. of Terminals: 20; Package Code: QCCN; Package Shape: SQUARE;
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian 54ACT11020FK 148
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote

    Texas Instruments 54ACT11020J

    NAND GATE; Temperature Grade: MILITARY; Terminal Form: THROUGH-HOLE; No. of Terminals: 14; Package Code: DIP; Package Shape: RECTANGULAR;
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian 54ACT11020J 88
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote

    54ACT11020 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    54ACT11020 Texas Instruments DUAL 4-INPUT POSITIVE-NAND GATES Original PDF
    54ACT11020 Texas Instruments DUAL 4-INPUT POSITIVE-NAND GATES Original PDF
    54ACT11020FK Texas Instruments DUAL 4-INPUT POSITIVE-NAND GATE Original PDF
    54ACT11020J Texas Instruments DUAL 4-INPUT POSITIVE-NAND GATE Original PDF

    54ACT11020 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    54ACT11020

    Abstract: 74ACT11020 D2957
    Text: 54ACT11020, 74ACT11020 DUAL 4ĆINPUT POSITIVEĆNAND GATES ą ą SCAS016A − D2957, JUNE 1987 − REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to


    Original     		54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 54ACT11020 74ACT11020 D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11020, 74ACT11020 DUAL 4ĆINPUT POSITIVEĆNAND GATES ą ą SCAS016A − D2957, JUNE 1987 − REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to


    Original     		54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 PDF

    54ACT11020

    Abstract: 74ACT11020 D2957
    Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A – D2957, JUNE 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to


    Original     		54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 54ACT1102customer 54ACT11020 74ACT11020 D2957 PDF

    54ACT11020

    Abstract: 74ACT11020 D2957
    Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A – D2957, JUNE 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to


    Original     		54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mil 54ACT11020 54ACT1102ocal 54ACT11020 74ACT11020 D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout


    OCR Scan     		54ACT11020, 74ACT11020 TI0053-- 54ACT11020 74ACT11020 500-mA 300-mil PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - D2957, JUNE 1987 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible ■ ■ * Flow-Through Architecture to Optimize PCB Layout I I * Center-Pin V^c and GND Configurations to Minimize High-Speed Switching Noise


    OCR Scan     		54ACT11020, 74ACT11020 SCAS016A D2957, 54ACT11020. 500-mA 300-mil PDF

    54ACT11020

    Abstract: 74ACT11020 D2957 9n10
    Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D2957, JU N E 1987— REVISED JA N U A R Y 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 1 1020 . . . J P ACKA G E 7 4 A C T 11 0 20 . . . D OR N P ACKA G E Flow-Through Architecture to Optimize PCB


    OCR Scan     		54ACT11020, 74ACT11020 TI0053â D2957, 500-mA 300-mil 54ACT11020 74ACT11020 D2957 9n10 PDF

    CT1102

    Abstract: 54ACT11020 74ACT11020 D2957 692B
    Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout 54A C T11020. . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE TOP VIEW


    OCR Scan     		54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mll 54ACT11020. 74ACT11020 T4EC11 CT1102 54ACT11020 D2957 692B PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11020,74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - 02957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible 54ACT11020. . . J PACKAGE 74ACT11020. . . D OR N PACKAGE TOP VIEW Flow-Through Architecture to Optimize PCB Layout Center-Pin Vqc and GND Configurations to


    OCR Scan     		54ACT11020 74ACT11020 SCAS016A 500-mA 300-mil 54ACT11020. 74ACT11020. 54ACT11020 PDF