44TB5 Search Results

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEH S1E ] 44Tb5D3 0 0 n i 7 7 •HITS HB56D136B S eries-1,048,576-Word x 36-Bit High Density Dynamic RAM Module ■ DESCRIPTION ■ PIN OUT The HB56D136B is a 1 M x 36 dynamic RAM module, mounted 8 pieces of 4 Mbit DRAM HM514400JP sealed in

S300

Abstract: ZAG100A05 ZAG100A1 ZAG100A2 ZAG100A3 ZAG100A4 ZGA100A4 Hitachi Scans-001
Contextual Info: r 1HITACHI/-COPTOELECTRONICS} ♦ J> | 44clb5GS DOtnfllb S | ~ D T ’O h IS bû — K Suppression Diode ZAGÌODA o 1 DE | \- I 44Tb5DS Type Color of cathode band ZAG100A05 ZAG100A1 K - t f Symbol-^^ VRRM : 50V—400V PRM: 100W OOCHfllb S 03.5MAX. 29MIN.

Contextual Info: H I T A C H I / LOGIC/ARRAYS/HEtl TS D E I 44Tb503 0 0 1 0 4 5 1 1 | 92D HD74HC237 3-to-8-line Decoder/Demultiplexer with Address Latch The H D 7 4 H C 2 3 7 decodes a three-bit Addrejs to one-of-eight active-high output«. | The device hat a transparent latch for

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / N E f l E O E D • 4 4 ^ 2 0 3 0 0 l 4 7 b S HN27C301P/FP Series- T -W -13- I S 131072-word x 8-bit CMOS One Time Electrically Programmable ROM The HN27C301P Series are 131072-word x 8-bit one time electrically programmable ROM. Initially, all bits of the

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM TS 44^203 00104^ 3 HD74HC356 92D 7 | 10499 D 18-to-l-line Data Selector/M ultiplexer/Register with 3-state outputs) - T - b - 7 - 2 1 - £ 7 This data selectors/multiplexers contain full on-chip binary

Contextual Info: HITACH I/ L O G I C / A R R A YS/MEH ^5 HD74HC292 HD74HC294 This device divides the j>Ê| 44TL.S03 00104fll □ 92D 10481 incoming clock frequency by a | PIN ARRANGEMENT •H D 7 4 H C 2 9 2 inputs. It has tw o Clock inputs, either o f which m ay be used as a clock in hib it. The device also has an active-low Reset,

Contextual Info: HI T A C H I / 1 E | M4Tt.ED3 D O l O b S E LOGIC/ARRAYS/riEM T2 HD74HCT245 92D 10652 I T 'S 2 ~ 3 / # Octal Bus Transceivers with 3-state outputs) This device has an active low enable input G and a direction control input (DIR). When D IR is high, data flows from the

Contextual Info: HITACHI/ L O G IC /A RRAY S/ MEN IE D E | 4 4 ^ 2 0 3 DGlDSMI 1 |~~ 92D 10549 HD74HC593 8-bit R egister/B in ary Counter w ith 3 -s ta te I/O The HD74HC593 consists of a parallel input, 8-bit storage register feeding an 8*bit binary counter. Both the register

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEU TE D E I 4 4 cit.EGB 0 0 1 0 M S 3 92D HD74HC238 5 10453 D 3-to-8-line Decoder/Demultiplexer The H D 7 4 H C 2 3 8 hat 3 binary select Inputs A, B, and C . | PIN ARRANGEM ENT If the device It enabled thete Inputs determine which one of

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

Contextual Info: Section 1 H8S/2245 Series Features 1.1 H8S/2245 Series Functions H8S/2245 Series microcomputers are designed for faster instruction execution, using a realtime control oriented CPU with an internal 32bit architecture, and can run programs based on the C high-level language efficiently. As well as large-capacity ROM and RAM, these microcomputers

Contextual Info: HM62W8128 Seríes Product Preview 131072-Word x 8-Bit High Speed CMOS Static RAM Ordering Information Description Typ e No. A ccess tim e H M 62W 8128LP-10 100 ns H M 62W 8128LP-12 120 ns H M 62W 8128LP-1O L 100 ns H M 6 2W 81 28 LP-12 L 120 ns H M 62W 8128LP-1O SL

Contextual Info: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description T he H itachi H M 5118160B I is a C M O S dynam ic R A M organized as 1,048,576-w ord x 16-bit. It em ploys the m ost advanced C M O S technology fo r high perform ance and low pow er. T he H M 5118160B I offers

Contextual Info: Section 19 Electrical Characteristics 19.1 Absolute Maximum Ratings Absolute Maximum Ratings Symbol Rating Unit Power supply voltage < o o Table 19.1 Item -0 .3 to +7.0 V Program voltage Vpp -0 .3 t o +13.5 V Input voltage Vin —0.3 to V çq + 0.3 V Operating temperature

D6346

Contextual Info: HITAC H I/ MCU/nPU DeT| 4 4 ^ 5 0 4 4496204 HITACHI/ MCU/MPU 92D 12452 HD63463-H D C H a r d Disk Controller DESCRIPTION The HD63463 (HDC: Hard Disk Controller) is a CMOS device developed for use as a peripheral L S I for the 16-bit microprocessor HD68000 (M PU: Microprocessing U nit). The

404829

Abstract: HD404829FS HD404829 441L204 06E 906 051 K
Contextual Info: H D 404829 S e r ie s Description The HD404829 Series is an HMCS400-series microcomputer designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an LCD controller/driver, A/D converter, input capture circuit, 32-kHz oscillator for clock use, and four

Contextual Info: HM514405C Series Preliminary 1,048,576-word x 4-bit Dynamic Random Access Memory HITACHI The H itachi H M 514405C is a CMOS dynam ic RA M o rg a n iz e d 1 ,0 4 8 ,5 7 6 w ords x 4 b its. HM514405C has realized higher density, higher performance and various functions by employing

00534

Abstract: GD234
Contextual Info: b lE H M D 5 1 1 6 4 1 0 • S MMTbPOB e r ie s 0023404 BBT H IT A C H I/ ■ H I T S l o g i c /A R R A Y S / M E M 4,194,304-word x 4-bit Dynamic Random Access Memory T he H M 5116410 is a CM OS d y n am ic RAM organized 4,194.304 words x 4 bits. It employs the

HM5241

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM blE J> m 44Sb203 DG23fl71 b77 • H I T S HM 5216800 S e rie s HM 5416800 S e rie s Prelim inary 1,043,576-worû x 8-bit x 2-bank Synchronous Dynamic RAM 0 HITACHI AH inputs and outputs are referred to the rising edge o f the clo ck in p u t. T he H M 5216800

HD44237C

Abstract: 1g52 HD44238C hd44235
Contextual Info: HITACHI/ {LINEAR DEVICES} Ta I I ‘ M i k a a s 920 4 0010511 10511 D T -7 5 -//-0 ? HD44235C,HD44236C,-HD44237C,HD44238C Single Chip CODEC with Filters(COMBO • FEATURES o SINGLE CHIP CMOS CODEC WITH FILTER IN 16-pins DIL PACKAGE o POWER SUPPLY VOLTAGE + 5V+5%, LOW POWER DISSIPATION (50mW typ.)

2SJ110

Abstract: 2sj118 t1511
Contextual Info: bl E D • MMTbSGS 0D1ST17 570 ■ H I T M 2 S J118 , 2 S J110 H I T A C H I / OPTOELECTRONICS *3.!±02 SILICON P-CHANNEL MOS FET - HIGH SPEED POWER SWITCHING, HIGH FREQUENCY POWER AMPLIFIER Complementary pair with 2SK413, 2SK414 ■ FEATURES • Low On-Resistance.

Contextual Info: HM5216808C Series HM5216408C Series 1,048,576-word x 8-bit x 2-bank Synchronous Dynamic RAM SSTL-3 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM (SSTL-3) HITACHI ADE-203-617 (Z) Preliminary Rev. 0.0 Jul. 10, 1996 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5216808C Series,

Contextual Info: HB526C264EN-10IN, HB526C464EN-10IN 1.048.576-word x 64-bit x 2-bank Synchronous Dynamic RAM Module 1.048.576-word x 64-bit x 4-bank Synchronous Dynamic RAM Module HITACHI ADE-203-737A Z Rev. 1.0 Feb. 7, 1997 Description The HB526C264EN, HB526C464EN belong to 8-byte DIMM (Dual In-line Memory Module) family,

Contextual Info: HB56H232 Series, HB56H132 Series 2,097,152-word x 32-bit High Density Dynamic RAM Module 1,048,576-word x 32-bit High Density Dynamic RAM Module HITACHI ADE-203-700A Z Rev.1.0 Dec. 27, 1996 Description The HB56H232 is a 2M x 32 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM (HM5118165)