Untitled
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
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CY7C1352G
CY7C1352G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)
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CY7C1347G
CY7C1347G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)
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CY7C1347G
100-pin
119-ball
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Untitled
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times
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CY7C1327G
250-MHz
200-MHz
166-MHz
133-MHz
100-pin
119-ball
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AN54908
Abstract: CY7C1327G
Text: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description The CY7C1327G SRAM[1] integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are
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CY7C1327G
CY7C1327G
AN54908
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Untitled
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter
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CY7C1327G
CY7C1327G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)
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CY7C1347G
100-pin
119-ball
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CY7C1352G
Abstract: CY7C1352G-133AXC 419256 TQFP PACKAGE thermal resistance
Text: CY7C1352G 4-Mbit 256K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability
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CY7C1352G
CY7C1352G
CY7C1352G-133AXC
419256
TQFP PACKAGE thermal resistance
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Untitled
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter
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Original
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PDF
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CY7C1327G
CY7C1327G
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Untitled
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
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Original
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PDF
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CY7C1352G
133-MHz
100-pin
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Untitled
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description[1] • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
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Original
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PDF
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CY7C1352G
CY7C1352G
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CY7C1352G
Abstract: CY7C1352G-133AXC
Text: CY7C1352G 4-Mbit 256K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability
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CY7C1352G
CY7C1352G
CY7C1352G-133AXC
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A8299
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability
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Original
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CY7C1352G
250-MHz
200-MHz
166-MHz
133-MHz
100-pin
A8299
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165 ball
Abstract: CY7C1347G-133AXI AN1064 CY7C1347G
Text: CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • • • • • The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at
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CY7C1347G
CY7C1347G
165 ball
CY7C1347G-133AXI
AN1064
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CY7C1327G
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times
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CY7C1327G
250-MHz
100-pin
119-ball
CY7C1327G
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CY7C1327G
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Features Functional Description • Registered Inputs and Outputs for Pipelined Operation ■ 256K x18 common I/O Architecture ■ 3.3V Core Power Supply (VDD) ■ 2.5V I/O Power Supply (VDDQ) ■ Fast Clock-to-Output Times
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CY7C1327G
250-MHz
100-pin
119-ball
CY7C1327-support
CY7C1327G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Functional Description Features • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)
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Original
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PDF
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CY7C1347G
100-pin
119-ball
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Untitled
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
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Original
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PDF
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CY7C1352G
CY7C1352G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)
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Original
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PDF
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CY7C1347G
CY7C1347G
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Untitled
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter
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Original
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PDF
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CY7C1327G
CY7C1327G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K x 36 common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ)
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Original
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PDF
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CY7C1347G
250-MHz
100-Pin
119-Ball
165-Ball
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CY7C1327G
Abstract: No abstract text available
Text: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times
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Original
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PDF
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CY7C1327G
250-MHz
100-pin
119-ball
CY7C1327G
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Untitled
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
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Original
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PDF
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CY7C1352G
CY7C1352G
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CY7C1352G
Abstract: CY7C1352G-133AXC
Text: CY7C1352G 4-Mbit 256K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability
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Original
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CY7C1352G
CY7C1352G
CY7C1352G-133AXC
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