4 INPUT LUT Search Results
4 INPUT LUT Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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MHM411-21 | Murata Manufacturing Co Ltd | Ionizer Module, 100-120VAC-input, Negative Ion |
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P8243 |
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P8243 - Parallel I/O Port, 16 I/O, NMOS, PDIP24 |
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P8255A-5 |
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P8255A - Parallel I/O Port, 24 I/O, NMOS, PDIP40 |
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D8243 |
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8243 - Parallel I/O Port, 16 I/O, NMOS, CDIP24 |
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TD8243 |
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8243 - Parallel I/O Port, 16 I/O, NMOS, CDIP24 |
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4 INPUT LUT Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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TC4075BP
Abstract: TC4072BP TC40 TC4072 TC4072BF
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TC4075BP/BF TC4071BP/TC4071BF TC4072BP/TC4072BF TC4075BP/TC4075BF TC4071BP/BF, TC4075BP/BF TC4072BP/BF TC4071BP/BF 72BP/BF 75BP/BF TC4075BP TC4072BP TC40 TC4072 TC4072BF | |
Contextual Info: 60SHSZUUV Am 25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including: |
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Am25LS09 54LS/74LS399 Am25LS 440/xA Am25LS Am54LS/74LS 03701B | |
inverter pmi OP77
Abstract: AD7542BD AD7542AD 7542A l6530 PM7542 AABB PM7542EQ
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16-Pin) AD7542 AttenuMC6800 MC6800 inverter pmi OP77 AD7542BD AD7542AD 7542A l6530 PM7542 AABB PM7542EQ | |
IP00C753Contextual Info: IP00C753 IP00C753 Specifications INPUT 2 PORTS RGB or YUV4:4:4 30 bits @ 162 MHz YUV4:2:2 24 bits @ 162 MHz YUV4:2:2 10 bits @ 162 MHz (BT656 input) OUTPUT RGB or YUV4:4:4 30 bits @ 162 MHz FPD Link output, LVCMOS compatible IMAGE SIZE Channel 1: Up to 4096 pixels/line with 2048 active pixels max.* |
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IP00C753 IP00C753 BT656 12-bit 900-pin | |
T74LS40B1
Abstract: T54LS40D2 T74LS40
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T54LS40/T74LS40 T54LS40 T74LS40 T74LS40 T74LS40B1 T54LS40D2 | |
vhdl code for multiplexer 16 to 1 using 4 to 1 in
Abstract: MUX 4-1 verilog code for multiplexer 16 to 1 vhdl code for multiplexer 16 to 1 using 4 to 1 vhdl code for multiplexer 32 to 1 vhdl code for multiplexer 8 to 1 using 2 to 1 by design of 16-1 multiplexer vhdl code for multiplexers verilog code for multiplexer 2 to 1 B0110
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UG002 vhdl code for multiplexer 16 to 1 using 4 to 1 in MUX 4-1 verilog code for multiplexer 16 to 1 vhdl code for multiplexer 16 to 1 using 4 to 1 vhdl code for multiplexer 32 to 1 vhdl code for multiplexer 8 to 1 using 2 to 1 by design of 16-1 multiplexer vhdl code for multiplexers verilog code for multiplexer 2 to 1 B0110 | |
Contextual Info: T O SH IB A TC74VHC20F/FN/FT TO SH IBA CM OS D IGITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74VHC20F, TC74VHC20FN, TC74VHC20FT DUAL 4 -INPUT NAND GATE Note The JEDEC SOP (FN) is not available in Japan. The TC74VHC20 is an advanced high speed CMOS 4-INPUT |
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TC74VHC20F/FN/FT TC74VHC20F, TC74VHC20FN, TC74VHC20FT TC74VHC20 14PIN 200mil OP14-P-300-1 | |
MQFP-256
Abstract: MQFP256 ATFS450 MQFP352 ATF280F AT69170 ATF280 LGA rework ATF280F-YF-E D22W-1
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ATF280F MQFP-256 MQFP256 ATFS450 MQFP352 ATF280F AT69170 ATF280 LGA rework ATF280F-YF-E D22W-1 | |
SARS diode
Abstract: WM0834 WM0834CD WM0834CN WM0834IN WM0838 ADC0834 ADC0838 SARS 03 DIAGRAM
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WM0834, WM0838 WM0834 WM0838 WM0834/8 MS-001( MS-001) SARS diode WM0834CD WM0834CN WM0834IN ADC0834 ADC0838 SARS 03 DIAGRAM | |
Contextual Info: SDRAM MODULE Preliminary KMM377S3320T1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 4 (July 1998) - "REGE" description is changed. Revision 5 (November 1998) - Corrected DQ# at the input of SDRAM(D5) as DQ16-19 @Functional Block Diagram |
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KMM377S3320T1 DQ16-19 KMM377S3320T1 32Mx72 32Mx4, 377S3320T1 44S32030T | |
Contextual Info: DUAL 4-INPUT NAND GATE DESCRIPTION The T54LS22/T74LS22 is a high speed DUAL 4-INPUT NAND GATE fabricated in LOW POWER SCHOTTKY technology. 1 B1 Plastic Package D1/D2 Ceramic Package V* M1 Micro Package Cl Plastic Chip Carrier O R D E R IN G N U M B E R S : |
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T54LS22/T74LS22 T74LS22 T54LS22 | |
74hc11Contextual Info: SN54HC11, SN74HC11 TRIPLE 3-INPUT POSITIVE AND GATES D 2 6 6 4 . DECEM BER 1 9 82 These devices contain three independent 3-input AND gates. They perform the Boolean functions Y = A *B *C o r Y = A + B + C in positive logic. H H H H 12 > c c Die Zhv 2B L 4 |
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SN54HC11, SN74HC11 300-mil SN54HC11 74hc11 | |
PAL EncodersContextual Info: Multimedia ICs Digital NTSC Encoder BU1414AK This IC converts digital RGB input to analog video signals in the NTSC format. •Features 1 Supports 13.5MHz input clocks, ideal for NTSC video CDs 2) Input signal is RGB 24-bit 3) Master system compatible 4) Three channels NTSC, Y and C) are output via |
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BU1414AK PAL Encoders | |
ATF280F
Abstract: ATF280F-DK352 ATF280F-YF-E ATF280F-2J-E 32X4 IO937 ATF280F-DK U1 V1 and W1 is delta connections ATF280F-YF-MQ 115kBits
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ATF280F 7750D ATF280F-DK352 ATF280F-YF-E ATF280F-2J-E 32X4 IO937 ATF280F-DK U1 V1 and W1 is delta connections ATF280F-YF-MQ 115kBits | |
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ATF280
Abstract: IO393 ATF280F 32X4 ATF280F-DK352 ATF280F-DK atmel 2816 memory atmel 841 ATF280FKA-MQ ATF280F-DK472
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ATF280FFeatures 7750B ATF280 IO393 ATF280F 32X4 ATF280F-DK352 ATF280F-DK atmel 2816 memory atmel 841 ATF280FKA-MQ ATF280F-DK472 | |
MAX7239
Abstract: I2708 MAX7231 i 2708
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MAX7231/32/33/34 MAX7231 MAX7232 MAX7233 MAX7234 AX723! AX7232 UAX7234 MAX7239 I2708 i 2708 | |
i-Chips Technology
Abstract: IP00C762
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IP00C763 IP00C763 60-bit/YUV4 60-bit 81MHz 36-bit/YUV4 24-bit/YUV4 10-bit 162Mhz i-Chips Technology IP00C762 | |
Contextual Info: SDRAM MODULE Preliminary KMM377S3323T Revision History Revision 1 M ay 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 2 (July 1998) - "REGE" description is added. Revision 3 (Aug. 1998) - Three ALVC 162835 & one CDC2509A are used. Revision 4 (Sep. 1998) |
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KMM377S3323T CDC2509A CDC2509B 12pF/5pF KMM377S3323T 16Mx8, 377S33 | |
F4804
Abstract: F4804-R Q48T30033
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F4804 F4804-R Q48T30033 | |
FW100S4R0
Abstract: FW150S4R0 FW150S4R09
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FW100S4R0 FW150S4R0 FW100S4R09 FW150S4R09 005002b | |
mb 8719
Abstract: 004II
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FW100S4R0 FW150S4R0 FW100S4R09 FW150S4R09 005002b mb 8719 004II | |
Contextual Info: Lucent Technologies Bell Labs Innovations FW100S4R0 and FW150S4R0 Power Modules: dc-dc Converters; 36 to 72 Vdc Input, 4 Vdc Output; 80 W to 120 W Features • Wide input range ■ High efficiency: 82% typical ■ Parallel operation with load sharing ■ Low profile: 12.7 mm 0.5 in. |
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FW100S4R0 FW150S4R0 FW100S4R09 FW150S4R09 003002b | |
ip00cContextual Info: IP00C811 IP00C811 Specifications INPUT 2 PORTS • 30-bit RGB/YUV 4:4:4 @ 166 MHz • 20-bit/10 bit YUV 4:2:2 @ 166 MHz EMBEDDED ANALOG FRONT-END • Video decoder for NTSC/PAL/SECAM • Supports Composite (CVBS) and S-Video inputs • 10-bit ADC • Adaptive Comb filter for Y/C separation |
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IP00C811 IP00C811 30-bit 20-bit/10 10-bit RGB/30-bit 4/20-bit 900-pin ip00c | |
Contextual Info: Data Sheet June 1999 microelectronics group Lucent Technologies Bell Labs Innovations ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 pm OR3C and 0.3 pm (OR3T) 4-level metal technology, (4- or 5-input |
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GD3T75fci |