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    AS6C1008

    Abstract: AS6C1008-55
    Text: February 2007 AS6C1008 128K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time :55ns Low powe r consumption: Operating current:10 mA TYP. Standby current: 1 µA (TYP.) Single 2.7V ~ 5.5V po we r supply Fully Compatible with all Competitors 5V product


    Original     		PDF AS6C1008 32-pin 36-ball AS6C1008 02/February/07, AS6C1008-55

    CY7C1059DV33

    Abstract: CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI
    Text: PRELIMINARY CY7C1059DV33 8-Mbit 1M x 8 Static RAM Functional Description[1] Features • High speed — tAA = 10 ns The CY7C1059DV33 is a high-performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an


    Original     		PDF CY7C1059DV33 CY7C1059DV33 CY7C1059DV33-10BAXI CY7C1059DV33-10ZSXI

    Untitled

    Abstract: No abstract text available
    Text: bq24260 bq24261 bq24262 www.ti.com SLUSBA2A – MARCH 2013 – REVISED OCTOBER 2013 3A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support Check for Samples: bq24260, bq24261, bq24262


    Original     		PDF bq24260 bq24261 bq24262 36-ball QFN-24

    Untitled

    Abstract: No abstract text available
    Text: TPS65200 www.ti.com SLVSA48 – APRIL 2010 LI+ BATTERY CHARGER WITH WLED DRIVER AND CURRENT SHUNT MONITOR Check for Samples: TPS65200 FEATURES 1 • • • • • • • • • • • • • Battery Switching Charger, WLED Driver, and Current Shunt Monitor in a Single Package


    Original     		PDF TPS65200 SLVSA48

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.9, April 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features  Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode


    Original     		PDF iCE40â DS1040 iCE40 DS1040 LP384

    Untitled

    Abstract: No abstract text available
    Text: bq24260 bq24261 bq24262A www.ti.com SLUSBU4 – DECEMBER 2013 3A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support Check for Samples: bq24260, bq24261, bq24262A FEATURES – Thermal Regulation Protection for Input


    Original     		PDF bq24260 bq24261 bq24262A

    Untitled

    Abstract: No abstract text available
    Text: CY62138EV30 MoBL ® 2-Mbit 256 K x 8 MoBL Static RAM 2-Mbit (256 K × 8) MoBL® Static RAM Features Functional Description • Very high speed: 45 ns ❐ Wide voltage range: 2.20 V to 3.60 V The CY62138EV30 is a high performance CMOS static RAM organized as 256K words by eight bits. This device features


    Original     		PDF CY62138EV30

    Untitled

    Abstract: No abstract text available
    Text: CY62138FV30 MoBL 2-Mbit 256 K x 8 Static RAM 2-Mbit (256 K × 8) Static RAM Features Functional Description • Very high-speed: 45 ns The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This


    Original     		PDF CY62138FV30

    V62C2804096

    Abstract: No abstract text available
    Text: MOSEL VITELIC PRELIMINARY V62C2804096 512K X 8, CMOS STATIC RAM Features Description • ■ ■ ■ ■ ■ ■ ■ The V62C2804096 is a very low power CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW


    Original     		PDF V62C2804096 V62C2804096 32-Pin 36-Ball Blo081

    T14L1024N

    Abstract: T14L1024N-10C T14L1024N-10H T14L1024N-10J T14L1024N-10P T14L1024N-10W
    Text: tm TE CH T14L1024N SRAM 128K X 8 HIGH SPEED CMOS STATIC RAM FEATURES GENERAL DESCRIPTION • Fast Address Access Times : 10/12/15ns The T14L1024N is a one-megabit density, fast static random access memory organized as 131,072 words by 8 bits. It is designed for


    Original     		PDF T14L1024N 10/12/15ns T14L1024N 110/105/100mA 32thout 36-Ball 8x10mm) T14L1024N-10C T14L1024N-10H T14L1024N-10J T14L1024N-10P T14L1024N-10W

    LCMXO2-1200HC-4TG100C

    Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
    Text: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1


    Original     		PDF HB1010 LCMXO2-1200HC-4TG100C LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC

    35x45mm

    Abstract: 6X6 mlp
    Text: FIN212AC 12-Bit Serializer Deserializer with Multiple Frequency Ranges Features Description ƒ ƒ ƒ ƒ ƒ ƒ Low Power Consumption The FIN212AC µSerDes is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 12-bit data path to


    Original     		PDF FIN212AC 12-Bit FIN212AC 35x45mm 6X6 mlp

    Untitled

    Abstract: No abstract text available
    Text: Preliminary‡ MT9V112 - 1/6-Inch SOC VGA Digital Image Sensor Features 1/6-Inch SOC VGA CMOS Digital Image Sensor MT9V112I2ASTC For the latest data sheet, refer to Micron’s Web site: www.micron.com/imaging Features Table 1: • DigitalClarity CMOS imaging technology


    Original     		PDF MT9V112 MT9V112I2ASTC 09005aef8154a39d/Source: 09005aef8175e6cc

    TSOP32 pad

    Abstract: bs62lv1027 R0201-BS62LV1027
    Text: Very Low Power CMOS SRAM 128K X 8 bit BS62LV1027 Pb-Free and Green package materials are compliant to RoHS n FEATURES n DESCRIPTION Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 18mA Max. at 55ns


    Original     		PDF BS62LV1027 BS62LVontinued) R0201-BS62LV1027 TSOP32 pad bs62lv1027 R0201-BS62LV1027

    LY621024

    Abstract: LY621024SL LY621024LL 128K X 8 BIT LOW POWER CMOS SRAM
    Text:  LY621024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.6 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Description Initial Issue Revised sym. b of 32 pin 450mil SOP package outline dimension in page 8 Added SL C-grade Spec.


    Original     		PDF LY621024 450mil 32-pin 36-ball LY621024 LY621024SL LY621024LL 128K X 8 BIT LOW POWER CMOS SRAM

    LY62L1024

    Abstract: 128K X 8 BIT LOW POWER CMOS SRAM
    Text:  LY62L1024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Revised Icc Deleted L grade Added SL grade Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free


    Original     		PDF LY62L1024 32-pin 36-ball LY62L1024 128K X 8 BIT LOW POWER CMOS SRAM

    29IO1

    Abstract: A62S6308 bga 6x8 Package bga 6x8
    Text: A62S6308 Series 64K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 64K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 1.0 Initial issue September 01, 1997 Preliminary 1.1 Modify TSOP TSSOP pin configuration. January 16, 1998


    Original     		PDF A62S6308 32-pin 36-ball 29IO1 bga 6x8 Package bga 6x8

    Untitled

    Abstract: No abstract text available
    Text: LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Description Initial Issue Revised Package Outline Dimension TSOP-II Revised ICC and ISB1 Revised Test Condition of ISB1/IDR


    Original     		PDF LY61L5128 36-ball

    LY621024PL-70LL

    Abstract: LY621024PL
    Text:  LY621024 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.8 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Description Issue Date Initial Issue Jul.25.2004 Revised sym. b of 32 pin 450mil SOP package outline dimension Jan.17.2007


    Original     		PDF LY621024 450mil LY621024GL-70LLE LY621024GL-70LLET LY621024GL-70LLI LY621024GL-70LLIT LY621024PL-70LL LY621024PL

    Untitled

    Abstract: No abstract text available
    Text:  LY62W2568 256K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Description Initial Issue Revised VIH to TTL compatible Revised IDR TYP. Revised VIH to 0.7*Vcc Revised VDR


    Original     		PDF LY62W2568 page9/10/12/13 32-pin 36-ball

    Untitled

    Abstract: No abstract text available
    Text: CY7C1059DV33 8-Mbit 1M x 8 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 110 mA at f = 100 MHz ■ Low CMOS standby power ❐ ISB2 = 20 mA The CY7C1059DV33 is a high performance CMOS Static RAM


    Original     		PDF CY7C1059DV33 CY7C1059DV33

    Untitled

    Abstract: No abstract text available
    Text: TPS65200 www.ti.com SLVSA48 – APRIL 2010 LI+ BATTERY CHARGER WITH WLED DRIVER AND CURRENT SHUNT MONITOR Check for Samples: TPS65200 FEATURES 1 • • • • • • • • • • • • • Battery Switching Charger, WLED Driver, and Current Shunt Monitor in a Single Package


    Original     		PDF TPS65200 SLVSA48

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.5, August 2013 iCE40 LP/HX Family Data Sheet Introduction August 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device


    Original     		PDF iCE40â DS1040 iCE40 DS1040 Distribut2013

    Untitled

    Abstract: No abstract text available
    Text: iCE40 LP/HX Family Data Sheet DS1040 Version 02.4, July 2013 iCE40 LP/HX Family Data Sheet Introduction July 2013 Data Sheet DS1040  Flexible On-Chip Clocking Features • Eight low-skew global clock resources • Up to two analog PLLs per device  Flexible Logic Architecture


    Original     		PDF iCE40â DS1040 iCE40 DS1040