32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Search Results

32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Result Highlights (5)

Part	Manufacturer	Description
TMPM3HNFDBFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002
TMPM3HPF10BDFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001
TMPM3HNF10BFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002
TMPM3HMF10BFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003
TMPM3HNF10BDFG	Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-QFP100-1420-0.65-003

32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
T9000 Abstract: STC104 IMST900-F20S IMST9000 inmos T9000 IMS processor inmos transputer reference manual Text: IMS T9000 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H Workspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit	Original	T9000 16Kbyte T9000 STC104 IMST900-F20S IMST9000 inmos T9000 IMS processor inmos transputer reference manual	PDF
RC3041 Abstract: RC32364 RC4640 RC4650 Text: RC32364 RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300 HDWXU WXUHV ◆ – Variable number of locked entries – No performance penalty for address translation ◆ Flexible bus interface allows simple, low-cost designs – Bus interface runs at a fraction of pipeline rate	Original	RC32364TM 32-bit RISCore32300 32-bit 133MHz 200mW 144-pin 79RC32 IDT79RC32V364 RC3041 RC32364 RC4640 RC4650	PDF
bta 137 Abstract: No abstract text available Text: RC32364 RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300 ◆ – Variable number of locked entries – No performance penalty for address translation ◆ Flexible bus interface allows simple, low-cost designs – Bus interface runs at a fraction of pipeline rate	Original	32-bit RISCore32300 RC32364TM RISCore32300TM 133MHz 180MHz 144-pin 79RC32 bta 137	PDF
Untitled Abstract: No abstract text available Text: ◆ ◆ TM High-performance embedded RISController microprocessor, based on IDT RISCore32300TM 32-bit CPU core Based on MIPS-II RISC architecture with enhancements Scalar 5-stage pipeline minimizes branch and load	Original	RISCore32300TM 32-bit 133MHz 133MHz 144-pin 79RC32 IDT79RC32V364	PDF
00FF Abstract: 06FFFFFF cache of translation lookaside buffer content Text: Chapter 3 Memory Management Unit / Caches 3.1 MMU OVERVIEW The MMU, which conforms to the SPARC Reference MMU Architecture, provides three primary functions: • Performs address translations from virtual addresses of each running process to physical addresses in physical	Original		PDF
CISC dan RISC Abstract: PDP-11 alpha 600 manual instruction 21164a Text: Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor A new CMOS microprocessor, the Alpha 21164, reaches 1,200 mips/600 MFLOPS peak performance . This new implementation of the Alpha architecture achieves SPECint92/SPECfp92	Original	300-MHz 64-bit mips/600 SPECint92/SPECfp92 64-bit CISC dan RISC PDP-11 alpha 600 manual instruction 21164a	PDF
alpha date code System Abstract: branch conditional unconditional instruction Text: Digital Semiconductor Alpha 21164 Microprocessor Product Brief March 1995 Description The Alpha 21164 microprocessor is a high-performance implementation of Digital’s Alpha architecture designed for application servers and high-performance clients. It has a superscalar design capable of issuing four instructions every clock	Original	64-bit alpha date code System branch conditional unconditional instruction	PDF
32 bit carry select adder code Abstract: MPC603E MPC603e FPU 32-bit microprocessor architecture detail of half adder ic microprocessor architecture programming Power motorola microprocessor 32 bit SR15 Text: Freescale Semiconductor, Inc. Technical Summary MPC603E/D Rev. 2 11/2001 Freescale Semiconductor, Inc. MPC603e RISC Microprocessor Technical Summary This document provides an overview of features for the MPC603e microprocessor and PowerPC architecture, and information about how the MPC603e implementation complies	Original	MPC603E/D MPC603e 0007t PID7t-603e) PID6-603e) 32 bit carry select adder code MPC603e FPU 32-bit microprocessor architecture detail of half adder ic microprocessor architecture programming Power motorola microprocessor 32 bit SR15	PDF
16 BIT ALU design structural Abstract: No abstract text available Text: Chapter 2 TurboSPARC Architecture 2.1 INTEGER UNIT AND FLOATING POINT CONTROLLER The integer unit IU and floating point control (FPC) are merged into a 9-stage pipeline. Below are some of the features of the IUFPC. • 9 stage instruction pipeline. • No branch folding. Branch instructions (taken/non-taken) execute in one cycle.	Original		PDF
SR15 Abstract: No abstract text available Text: Technical Summary MPC603E/D Rev. 2 11/2001 MPC603e RISC Microprocessor Technical Summary This document provides an overview of features for the MPC603e microprocessor and PowerPC architecture, and information about how the MPC603e implementation complies with the architectural definitions. Note that the MPC603e microprocessor is implemented in	Original	MPC603E/D MPC603e 0007t PID7t-603e) PID6-603e) SR15	PDF
prom 123 Abstract: C21x GF9101 IN17 IN18 IN19 Text: MultiGEN GF9101 High Performance Multirate Digital Filter DATA SHEET DESCRIPTION • highly optimized & flexible architecture for multirate FIR filtering applications The GF9101 is a high performance multirate digital filter which can be programmed to implement a wide range of	Original	GF9101 12-tap oper489, C-101, prom 123 C21x IN17 IN18 IN19	PDF
XC1736 Abstract: GF9101 IN17 IN18 IN19 pipelined adder Text: 0XOWLGEN GF9101 High Performance Multirate Digital Filter DATA SHEET • highly optimized & flexible architecture for multirate FIR filtering applications The GF9101 is a high performance multirate digital filter which can be programmed to implement a wide range of	Original	GF9101 12-tap C-101, XC1736 IN17 IN18 IN19 pipelined adder	PDF
Untitled Abstract: No abstract text available Text: 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H W orkspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit H 16 Kbyte instruction and data cache	OCR Scan	16Kbyte T9000 IMST900-F20S T9000	PDF
T9000 Abstract: STC104 STC104s Text: 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H Workspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit H 16 Kbyte instruction and data cache	OCR Scan	16Kbyte T9000 STC104 STC104s	PDF

Intel i860 Abstract: No abstract text available Text: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per	OCR Scan	64-BIT 128-Bit 32-Bit 32/64-Bit 80860XR Intel i860	PDF
FGT 313 Abstract: No abstract text available Text: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for	OCR Scan	64-BIT lntel386TM/486TM 168-pin 128-Bit 80860XR FGT 313	PDF
Untitled Abstract: No abstract text available Text: in te * MILITARY i860 64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for	OCR Scan	64-BIT /i486TM	PDF
Untitled Abstract: No abstract text available Text: i860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design — 25/33.3/40 MHz Clock Rates	OCR Scan	64-BIT 128-Bit 32-Bit 32/64-Bit	PDF
intel i860 Abstract: A80860XR-40 pbit 2180 a80860xr-33 A80860XR40 TE 2197 transistor 8550 sad intel I860 processor pin diagram of XR 2206 i860 64-Bit Microprocessor Performance Brief Text: i860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock ' — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design — 25/33.3/40 MHz Clock Rates	OCR Scan	64-BIT 128-Bit 32-Bit 32/64-Bit intel i860 A80860XR-40 pbit 2180 a80860xr-33 A80860XR40 TE 2197 transistor 8550 sad intel I860 processor pin diagram of XR 2206 i860 64-Bit Microprocessor Performance Brief	PDF
00A75 Abstract: INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860 Text: P K H IL D fiflD M M V MILITARY i860 XR 32/64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design	OCR Scan	i860TM 32/64-BIT 64-Bit 128-Bit 32-Bit CG/SALE/101789 00A75 INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860	PDF
FGT 313 Abstract: N06010 a3058c 271121 intel i860 Text: [ p fô iy iiM A O W in te L MILITARY i860 XR 32/64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Tw o Floating-Point Results per Clock High Perform ance Design	OCR Scan	64-Bit 128-Bit 32/64-B i860TM 32/64-BIT CG/SALE/101789 FGT 313 N06010 a3058c 271121 intel i860	PDF
Untitled Abstract: No abstract text available Text: r a iO M O G O M V Military ì860tm 64-Bit M icro p ro cesso r • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic — 386 /j 486TM Microprocessor Data Formats and Page Table Entries ■ Parallel Architecture that Supports Up	OCR Scan	860tm 64-Bit 486TM	PDF
ba 6414 fs Abstract: RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP Text: intei I860 XP MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction — Up to Two Floating-Point Results ■ High Performance Design — 40/50 MHz Clock Rate — 100 Peak Single Precision MFLOPS	OCR Scan	I860TM 64-Bit 128-Bit 32-Bit 32/64-Bit ba 6414 fs RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP	PDF
Untitled Abstract: No abstract text available Text: SÖE D ADVANCED MICRO DEVICES • 02S7S25 GQ332G^ 1 _ B g g g g g g T i j p -n-H L. _ Cl Advanced Micro Devices Am29005 Low-Cost Streamlined Instruction Microprocessor DISTINCTIVE CHARACTERISTICS ■ ■ ■ ■ ■ Full 32-blt, three-bus architecture	OCR Scan	02S7S25 GQ332G^ Am29005 32-blt, 16-MHz byte/half-word29005 QFP168 02S7525 QQ332T5	PDF

32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Search Results

32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Result Highlights (5)

32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Datasheets Context Search

T9000

RC3041

bta 137

Untitled

00FF

CISC dan RISC

alpha date code System

32 bit carry select adder code

16 BIT ALU design structural

SR15

prom 123

XC1736

Untitled

T9000

Intel i860

FGT 313

Untitled

Untitled

intel i860

00A75

FGT 313

Untitled

ba 6414 fs

Untitled